For the past few decades, System-on-Chip (SoC) has been the gold standard for optimizing the performance and cost of electronic systems. Pulling together practically all of a smartphone’s digital and analog capabilities into a monolithic chip, the mobile application processor serves as a near-perfect example of an SoC. But… Read More
Tag: 3d-ic
3D IC Update from User2User
Our smart phones, tablets, laptops and desktops are the most common consumer products with advanced 2.5D and 3D IC packaging techniques. I love seeing the product tear down articles to learn how advanced packaging techniques are being used, so at the User2User conference in Santa Clara I attended a presentation from Tarek Ramadan,… Read More
Bespoke Silicon is Coming, Absolutely!
It was nice to be at a live conference again. DesignCon was held at the Santa Clara Convention Center, my favorite location, which to me there was a back to normal crowd. The sessions I attended were full and the show floor was busy. Masks and vaccinations were not required, maybe that was it. Or there was a pent-up demand to get back engaged… Read More
Overcoming System-Level 3D-IC Electrical and Thermal Challenges
Overview
Electronics products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise.
Addressing these concerns through simulation during system planning and continuing through signoff will accelerate… Read More
Overcoming System-Level 3D-IC Electrical and Thermal Challenges
Overview
Electronics products with 3D-ICs face growing system challenges related to signal, power, and thermal integrity. Design density can lead to performance issues caused by heat, crosstalk, and power noise.
Addressing these concerns through simulation during system planning and continuing through signoff will accelerate… Read More
3D-IC Chip-Centric Power and Thermal Integrity with High-Performance Hiearchical Analysis
Overview
A 3D-IC includes the package, interposer, multiple chiplets, through-silicon vias (TSVs), and through-dielectric vias (TDVs). Supplying power to the chiplets and dissipating heat through these various components poses a major power integrity (PI) and thermal integrity challenge. Early analysis also is extremely… Read More
System Planning and Implementation for Different 3D-IC Design Styles
March 9, 2022
Overview
System planning is a major part of the multi-chiplet design. Whether it’s a 2.5-D configuration with an interposer or full-stacked 3D design mounted on a package, it is important to have an automated way to do bump assignment and optimization along with 3D structures implementation. With methodology evolving
More Than Moore and Charting the Path Beyond 3nm
The incredible growth that the semiconductor industry has enjoyed over the last several decades is attributed to Moore’s Law. While no one argues that point, there is also industry wide acknowledgment that Moore’s Law started slowing down around the 7nm process node. While die-size reductions still scale, performance jumps… Read More
Ansys CEO Ajei Gopal’s Keynote on 3D-IC at Samsung SAFE Forum
System on chip (SoC) based design has long been recognized as a powerful method to offer product differentiation through higher performance and expanded functionality. Yet, it comes with a number of limitations, such as high cost of development. Also, SoCs are monolithic, which can inhibit rapid adaptation in the face of changing… Read More
Ansys Multiphysics Platform
Background
Traditionally, the interface between chip designers and system power, packaging, reliability, and mechanical engineering teams was a relatively straightforward exchange of specifications. Chip designers developed preliminary power dissipation estimates, often based on a simplifying power/mm**2 value. … Read More