WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 725
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 725
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
    [is_post] => 
)
            
800x100 SNPS Intel Webinar 6 5 25 High Quality (1) (2)
WP_Term Object
(
    [term_id] => 14
    [name] => Synopsys
    [slug] => synopsys
    [term_group] => 0
    [term_taxonomy_id] => 14
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 725
    [filter] => raw
    [cat_ID] => 14
    [category_count] => 725
    [category_description] => 
    [cat_name] => Synopsys
    [category_nicename] => synopsys
    [category_parent] => 157
    [is_post] => 
)

Searching an ADC (or DAC) at 28 nm may be such a burden…

Searching an ADC (or DAC) at 28 nm may be such a burden…
by Eric Esteve on 09-09-2013 at 9:13 am

If you have ever send a Request For Quotation (RFQ) for an ASIC including processor IP core, memories, Interfaces IP like PCIe, SATA or USB and Analog function like Analog to Digital Converter (ADC) or Digital to Analog Converter (DAC), you have discovered, like I did a couple of years ago, that these Analog functions may be the key… Read More


Test Compression and Hierarchy at ITC

Test Compression and Hierarchy at ITC
by Daniel Payne on 09-09-2013 at 8:00 am

The International Test Conference (ITC) is this week in Anaheim and I’ve just learned what’s new at Synopsys with test compression and hierarchy. Last week I spoke with Robert Ruiz and Sandeep Kaushik of Synopsys by phone to get the latest scoop. There are two big product announcements today that cover:… Read More


Mobile SoC will benefit now from M-PCIe

Mobile SoC will benefit now from M-PCIe
by Eric Esteve on 08-27-2013 at 10:12 am

We have already discussed the recently released M-PCIe ECN from PCI-SIG in Semiwiki at the end of 2012, but the new “standard” (in fact an Engineering Change from PCI-SIG and MIPI Alliance) was only real on paper, at that time. The upcoming webinar from Synopsys, M-PCIe: Utilizing Low-Power PCI Express in Mobile Designs, shows … Read More


LSI’s Experience With Formality Ultra

LSI’s Experience With Formality Ultra
by Paul McLellan on 08-26-2013 at 5:36 pm

LSI is an early adopter of Formality Ultra, Synopsys’s tool for improving the entire ECO flow. I already wrote about the basic capability of the tool here. ECOs are changes that come very late in the design cycle, after place and route has already been “nearly” completed. They occur either due to last minute spec… Read More


More to the story than bigger FPGA-based prototyping

More to the story than bigger FPGA-based prototyping
by Don Dingee on 08-19-2013 at 5:00 pm

Still not convinced on the value of FPGA-based prototyping systems, or using older technology? I’ve been trying to find the story beyond just bigger, badder FPGAs in a box that you pour RTL into – and found some hints in a webinar on the Synopsys HAPS-70 from earlier this year.… Read More


Why Adopt Hierarchical Test for SoC Designs

Why Adopt Hierarchical Test for SoC Designs
by Daniel Payne on 08-15-2013 at 4:37 pm

IC designers have been creating with hierarchy for years to better manage large design sizes, however for the test world the concept of hierarchy and emerging standards is a bit newer. TSMC and Synopsys jointly created a webinarthat addresses hierarchical test, so I’ve attended it this week and summarized my findings here.… Read More


How to Benchmark a Processor

How to Benchmark a Processor
by Paul McLellan on 08-15-2013 at 2:11 am

How do you benchmark a processor? It seems like it should be easy, just run some code and see how fast it is. Traditionally processors were indeed benchmarked by raw performance like GMACS, GFLOPS, memory bandwidth and so on. But in today’s world where systems have become very complex and applications very compute intensive, the… Read More


Pre-verified, Integrated Sensor IP Subsystem?

Pre-verified, Integrated Sensor IP Subsystem?
by Eric Esteve on 07-31-2013 at 11:16 am

Last year, I said that the launch of ARC based complete sound system IP by Synopsys ring the bell for the opening of a new IP market segment, the “Subsystem IP”. This week, Synopsys has announced the availability of the DesignWare® Sensor IP Subsystem, a complete and integrated hardware and software solution for sensor control applications.… Read More


♫ IMG Sitting on the DOK of the Bay…Closin’ Timin’

♫ IMG Sitting on the DOK of the Bay…Closin’ Timin’
by Paul McLellan on 07-24-2013 at 7:00 am

Scott Fitzgerald is supposed to have said “the rich are not like other people” to Ernest Hemingway (he didn’t). In the same way, processors are not like other blocks, and not because they have more gates (they don’t). However, special approaches to optimizing processors are important because the clock… Read More


Debugging Verification Constraints

Debugging Verification Constraints
by Paul McLellan on 07-23-2013 at 3:44 pm

In his DAC keynote last year (2012) Mike Mueller of ARM compared how much CPU was required to verify the first ARM versus one of the latest ARM Cortex CPUs. Of course the newer CPU is hundreds of times larger than the first ARM but the amount of verification required was millions of times as much, requiring ARM to construct their own datacenter… Read More