Silicon Photonics – Back to the Future – Part Deux?

Silicon Photonics – Back to the Future – Part Deux?
by Mitch Heins on 04-10-2016 at 8:00 pm

I cut my teeth in silicon IC design at Texas Instruments during the early 1980’s working on what would eventually become the ASIC and Fabless IC industries that enabled the explosive growth of the electronics industry over the last three decades. Of late I’ve become involved in the silicon photonics space and I am getting an incredible sense of Deja vu. I’ve seen this movie before.

Silicon photonic design is at the same stage IC design was in the late 1970s. Most photonic IC (PIC) work is still taking place in labs with the few production parts coming from well-funded IDMs like Intel, IBM, ST Micro etc. The focus is mostly at the technology level figuring out how to make better devices. Design is still being done bottom up, not top down (e.g. layout a device, run TCAD simulations, fab some parts and see what happens). The question is how long will be it before silicon photonics really takes off and will it ever be as pervasive as electronics are today.

The good news for nascent technologies such as silicon photonics is that we are at a different starting point now then we were 30 years ago. IC Design methodologies have been codified and we have well understood business models and a mature ecosystem of specialized suppliers for CAD, fabrication, packaging and test. Yet, this very infrastructure could be the thing that holds silicon photonics back.

Case in point, how many big pure play foundries support silicon photonic  processes? Zero. Why? The simple answer is that the ecosystem has not only matured but it has been highly optimized for revenue and profit. Projected wafer demand for silicon photonics over the next couple of years is still in the 1000’s of wafers per year as compared to tens of thousands of CMOS wafers per month per fab in the electronics industry. The opportunity costs for running a photonics line in a pure play fab are very high. This however could change soon with the push towards “all optical” data centers and the introduction of embedded optics solutions. Yole’ Developpement predicts the silicon photonics market will grow at a CAGR of 38% from $25M in 2013 to $700M by 2024 (Yole’). They expect an inflection point in 2018 driven by four different applications: HPC, all-optical data centers, telecoms and sensors.

For now, research fabs such as imec, CEA-Leti, IME/A*STAR and a few others are carrying the load making multi-project wafer (MPW) runs available for companies looking to test their ideas. Most of these fabs are in Europe with exception of IME/A*STAR in Singapore. Recently the United States announced the formation of AIM (the American Institute for Manufacturing Integrated Photonics) to support silicon photonics by creating a National PIC manufacturing infrastructure center in the U.S. This is still in very early stages. Silicon photonic MPW services from the research fabs run on the order of ~$2K / mm[SUP]2[/SUP] as compared to ~$1K / mm[SUP]2[/SUP] for 0.13um CMOS logic. While the margins are higher, the low wafer volumes have not been attractive for commercial foundries to provide such MPW services. A good explanation of the current silicon photonics ecosystem can be found in a paper by Andy Eu-Jin Lim and team of IME covered in chapter 6 of the book Silicon Photonics III (Foundry Model Discussion).

There has been some movement on the fabless side with a collaboration started in 2011 between IME/A*STAR, GLOBALFOUNDRIES and Alcatel-Lucent to transfer the IME 25G silicon photonics platform to GF’s 200mm 0.18um CMOS foundry line. It is anticipated that their costs per mm[SUP]2[/SUP] for a Si PIC will be significantly less than for the research fabs although it’s not clear yet how that will translate to pricing and the capability has yet to come to market. At the same time, several technical differences between electronic and photonic processes have pushed the industry towards non-monolithic solutions. CMOS SOI is optimized for transistor performance while photonics SOI uses a much thicker buried oxide for optical loss reduction. Additionally, as dimensions of the electronics shrink there is a larger discrepancy between device dimensions of transistors (< 100nm) and photonic devices (0.1-1um). These differences plus the lack of a good light source on silicon have pushed the industry to look to hybrid electronic / photonic solutions that combine separate electronic and photonic die in a common package using 2.5D / 3D techniques. This allows for decoupling of technology nodes, substrate types, and wafer sizes while still enabling the use of CMOS compatible process equipment without the need to integrate two different process flows.

So, it appears that while we still have a journey ahead of us that momentum is growing for silicon photonics. I doubt I’ll see flying DeLorean cars in my lifetime but silicon photonics may let me relive again my journey through the birth of modern-day electronics.