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Solido
Posted on by Daniel Nenni

High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design!

High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design!
by Daniel Nenni on 11-01-2011 at 9:00 am
Categories: EDA, Foundries, Solido, TSMC

Hello Daniel,
I am very interested on the articles on the PVT simulation, I have worked in that area in the past when I worked in process technology development and spice modeling and I also started a company called Device modeling technology (DMT) which built a Spice model library of discrete components, such as Bipolar/MOS /POWER MOSFET/Analog Switch/ADC/CDA/PLL sold to companies like Fujitsu, Toshiba …etc.

We used to have a project when I worked on R&D to simulate the process based on the device architecture and send the out data to a simulator called PICE which is a device simulator and the output again was sent to the input of Spice simulator , as the Process simulator , the device simulator and spice simulator are connected.

We can easily define the performance of the targeted analog circuit with variation of process recipe and device structures, we can also predict the yield of each corner with running the spice PVT simulation against the six sigmal spice models. However, as you know, the performance always has to compromise with the reliability, and you can’t run the circuit simulation together with the reliability models, because no such models are available.

As a result I do not pay much attention to the result of spice simulation, because it can never tell you what the reliability will be with the result of spice simulation, and I still believe real corner lot wafer is the best way to verify the performance, yield and reliability.

Hi Edward,

Process variation is of great interest at 28nm and even more at 20nm. In a recent independent survey, variation-aware custom IC design was ranked the number one area requiring advancement over the next two years. The survey revealed:

[LIST=1]

  • 53% of design groups missed deadlines or experienced respins due to variation issues
  • Designers experienced an average 2 month delay due to variation issues
  • Designers spent an average 22% of design time on variation issues

    For further information, see the Gary Smith EDA analyst report on variation design.

    Here is a recent webinar done by Solido and TSMC on High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design.

    Attendees of this webinar learned:

    [LIST=1]

  • Variation challenges in custom IC design
  • Variation-aware solutions available in the TSMC AMS reference flow
  • Methods to develop and verify designs over PVT corners in less time
  • How to efficiently apply Monte Carlo techniques in design sign-off
  • How Monte Carlo is really possible up to 6-sigma
  • Customer case studies of the above methods

    Solido customer case studies include:

    [LIST=1]

  • NVIDIA for memory, standard cell, analog/RF design
  • Qualcomm for memory design
  • Huawei-HiSilicon for analog design
  • Qualcomm for I/O design
  • Anonymous for analog/RF design

    Presenters:

    [LIST=1]

  • Nigel Bleasdale, Director of Product Management, Solido Design Automation
  • Jason Chen, Design Methodology and Service Marketing, TSMC

    Audience: Circuit Designers, Design Managers, CAD Engineers

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