Key Takeaways
- Dr. Yuh-Jier Mii presented innovations in transistor architectures, including the transition from FinFET to Nanosheet and the development of CFET devices.
- TSMC successfully demonstrated its first CFET transistor at a 48nm gate pitch at IEDM 2023, achieving significant milestones in technology development.
- Progress has also been made with 2D channel materials, demonstrating efficient performance in stacked nanosheet architectures.
- Future plans include developing new interconnect technologies and materials to reduce resistance and improve performance.
The inaugural event for the 2025 TSMC Technology Symposium recently concluded in Santa Clara, California. This will be followed by events around the world over the next two months. We have summarized information from this event regarding process technology innovation and advanced packaging innovation. Overall, the A14 process node was deemed to define the most advanced technology available from TSMC. Recently, a presentation from the event was posted that discusses technology leadership, and in that presentation, what lies beyond A14. Seeing what’s around the next corner is always interesting. Let’s look at how TSMC describes technology innovation beyond A14.
The Presenter
The presenter was Dr. Yuh-Jier Mii, EVP and Co-Chief Operating Officer at TSMC. Dr. Mii is an excellent presenter. He describes very complex work in language everyone can understand. His presentation builds on work he presented at last year’s IEDM event. Dr. Mii covered a lot of information. A link is coming. But first, I’d like to focus on his comments on innovation at TSMC beyond A14.
What Was Said
The broad focus of Dr. Mii’s discussion focused on new transistor architectures and new materials. He began by discussing device architectures. The current evolution is from FinFET to Nanosheet. Beyond these technologies, vertically stacked NFET and PFET devices, called CFETs is a likely scaling candidate. Beyond CFET, there are breakthroughs in channel material that can enable further dimensional scaling and energy reduction. These developments are summarized in the graphic above.
Dr. Mii reported that TSMC has been actively building CFET devices on silicon to enable the next level of scaling. TSMC presented its first CFET transistor at a 48nm gate pitch at IEDM 2023. This year at IEDM, TSMC presented the smallest CFET inverter. The figure below illustrates the well-balanced performance characteristics of this device up to 1.2V.
He explained that this demonstration achieved a significant milestone in CFET technology development that will help to drive future technology scaling.
Dr. Mii reported that great progress has also been made on transistors with 2D channel materials. TSMC has demonstrated the first electrical performance using a monolayer channel in stacked nanosheet architecture similar to the N2 technology. An inverter has also been developed using well-matched N and P channel devices operating at 1V. This work is summarized in the figure below.
Going forward, there are plans to continue to develop new interconnect technologies to improve interconnect performance. For copper interconnect, the plan is to use a new via scheme to reduce via resistance and coupling capacitance. Work is also underway on a new copper barrier to reduce copper line resistance.
Beyond copper, there is work underway on new metal materials with an air gap that could further reduce resistance and coupling capacitance. Intercalated Graphene is another new and promising metal material that could significantly reduce interconnect delay in the future. This work is summarized in the graphic below.
To Learn More
Dr. Mii covered many other topics. You can view his entire presentation here. And that’s how TSMC describes technology innovation beyond A14.
Also Read:
TSMC Brings Packaging Center Stage with Silicon
TSMC 2025 Technical Symposium Briefing
IEDM 2025 – TSMC 2nm Process Disclosure – How Does it Measure Up?
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