TSMC: Keynote, OIP, 20nm, 16nm, panels, and more #51DAC

What is TSMC doing at DAC?

The biggest event is presumably Cliff Hou’s DAC keynote on Monday at 3.25pm Industry Opportunities in the Sub-10nm Era. And he also wrote the foreword to Fabless, the book that Dan Nenni and I have written and where you can get a signed copy on Tuesday evening at the reception.

There is an IP workshop Driving Quality to the Desktop of the DAC Engineer which takes place on Sunday from 1-5pm in room 202 in the Moscone Center. This is presented by Steven Chen and Lluis Paris.

TSMC is participating in two panels. The first is on the IP track and is in room 101. Lluis Paris is moderating the topic of IP Quality. There is also a pavilion panel on Connecting Everything: Architecting the Internet of Things,Dan K is on the panel.

There are lots of presentations with TSMC’s partners, too many to mention.

TSMC themselves are on booth 1801. They will be talking a lot about IP quality. Have you noticed TSMC are very big on IP quality? They started just using software tools such as Spyglass for evaluating quality but they have now created a silicon validation lab in Taiwan to take it to the next level.

So the top level message is:

• 20nm Complete

  • In mass production
  • Everything qualified and validated on customer designs
• 16nm FinFET Complete

  • V1.0 Certification completed
  • IP silicon validated and available
  • Interface IP in silicon validation now
  • 16nm FinFET will be ready by end of year

One new thing you might not have heard is that there is a new 28HPC process offering. Spice corners have been tightened and there is a new signoff methodology. There is also a new high-efficiency 7-track library.

OIP is thriving. It has been running for over 12 years. The portfolio is impressive with over 7000 titles from 40 different IP vendors.

Overview of activities is here. Theater schedule on the booth is here.

Once again, TSMC’s booth is #1801.

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