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U2U: Things You Might Not Know About TSMC

U2U: Things You Might Not Know About TSMC
by Paul McLellan on 04-10-2014 at 10:50 pm

 At Mentor’s U2U this afternoon I attended a presentation on TSMC’s use of Calibre PERC (it is a programmable electrical rule checker) for qualification of IP in TSMC’s IP9000 program. I’ve written about this before here. Basically IP providers at N20SOC, N16FF, and below are required to use PERC to guarantee ESD is OK. This is especially critical with FinFET since the transistors are more fragile and have a lower breakdown voltage. There are also decks for 28nm but it is not required (most IP is already in volume production so problems would have shown up by now). The PERC decks guarantee that the ESD rules are all checked without the error-prone process of having to manually add identifying layers. This is the first time TSMC has specified a particular tool that must be used.

Here is a random miscellany of other facts about TSMC that I picked up:

  • Risk production (samples) for 16FF was at the end of last year
  • Risk production for 10FF will be end of 2015
  • Lots of work has gone on on controlling capacitance on M1 and M2 at 16FF
  • 10nm will have triple patterning and spacer (sidewall image transfer I assume, self-aligned double patterning). More details on 10nm at the TSMC Technology Symposium on 22nd of April
  • TSMC has invested $10B a year for several years to get ready for FinFET
  • FinFET challenges:

    • parasitic capacitance due to the gate wrapping around the fin
    • high parasitic resistance due to local interconnect M0
    • quantized device sizes (only a certain number of fins)
    • breakdown voltage is lower so ESD is more of an issue
  • TSMC has 6600 registered IPs, adding 200 per month

    • 90% hard IP is qualified through IP9000
    • 100% of soft IP is qualified
    • One column on IP listing is (eg) 5/25000 meaning it has been in 5 tapeouts and 25,000 wafers of production
  • Extending from quality audit to slicon validation

    • TSMC has set up validation centere in Taiwan
    • over 20 IPs validated already (started with interface IP)
  • 28nm cycle time started as 4 months, now down to 2 months
  • 16nm cycle time is 5 months will probably end at 3 months
  • Currently 16FF shuttle is about 160 days
  • EUV, TSMC have invested $0.5B in ASML but ROI not good, keeps slipping. They are looking at e-beam and other backup strategies
  • Since EUV is certainly not coming soon, 3D technologies (CoWoS) very important

What is driving N16FF. Mobile of course. Here are the changes from 2012-2014

  • Display 2X
  • Radio 2X
  • Connectivity 3X
  • AP 2X CPU, 5X GPU and 2X memory bandwidth
  • 2 cores go to 8 cores
  • Power same or less
  • Form factor thinner and lighter
  • Camera 8MP to 13MP

If you are a TSMC customer you can register for the technology symposium on 4/22 here.
Details of Mentor’s European U2U in Munich on November 6th is here. You can still submit abstracts until July 1st.

More articles by Paul McLellan…

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