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TSMC Earthquake Damage Redo

TSMC Earthquake Damage Redo
by Daniel Nenni on 04-14-2010 at 10:54 pm
Categories: Foundries, TSMC

As you may know I enjoy poking fun at the current state of semiconductor design and manufacture media; sloppy reporting, editors with little or no actual semiconductor experience taking corporate marketing spins on news/events and passing it along as fact.

Last week it was the EETimes parroting the Samsung foundry business press. A nice thing about being a blogger and owning your own domain is that you get to see (Google Analytics) where the views come from and which links they click on etc…. It’s like spying on your siblings, not that I ever did that. Lets just say that last week South Korea discovered my blog.

This time it is the ElectronicsWeakly top viewed article TSMC Loses 40K Wafers In Quake by one of my fellow bloggers David Manners. There was a lot of press on this topic last week but David is the only one to put a number (40,000 wafers, which is significant) on the loss, and he led with it in an article versus his blog (insert sinister music here). The question is: Where did David get a 40,000 wafer loss number? Certainly not from the official TSMC press brief:

TSMC Reports Impact From March 4 Earthquake Initial Estimate of 1.5 Days Wafer Movement Loss
Issued by: TSMC Issued on: 2010/03/04 Hsinchu, Taiwan, R.O.C. – March 4, 2010 – TSMC (TWSE: 2330, NYSE: TSM) today announced that an earthquake of magnitude 6.4 on the Richter scale occurred in south Taiwan at 8:18 am Taiwan local time on March 4. The earthquake registered on instruments at TSMC’sTainansite at magnitude 5, and was measured at TSMC’s Hsinchu site at magnitude 2.

Current assessments reports show that the earthquake had minimal impact on Hsinchu fabs. WhileTainan fabs suffered greater impact, they have gradually begun to resume production. Our initial estimate is that the earthquake caused the equivalent of 1.5 days loss of wafer movement for the company in total.

Luckily one of my siblings, that I absolutely did not spy on when I was a kid, spent his career with semiconductor equipment manufacturers and knows of such things. He says that determining actual wafer or die loss in this context is next to impossibleand here is why:

There are 300+ steps in wafer production so the impact is spread over a long wafer movement process.Average wafer movement loss is calculated as: Each Fab’s Equipment Production Time Loss (including equipment check and recalibration) + Each Fab’s Wafer Scrap (wafers removed from the movement process and not returned) / by over all wafer movement for the company (TSMC). Average wafer movement loss is expressed in “days loss of wafer movement”, which is an averaged manufacturing index, not an actual wafer scrap or revenue loss number. Bottom line, you can’t determine actual “lost wafers” from “loss of wafer movement”.

It looks like David took TSMC’s 2009 capacity of 9,995,000 8-in wafers (the 8-in. equivalent number is used to normalize 6,8, and 12-in. wafer production) and divided it out using 1.5 days of “wafer movement loss” as “lost wafer production”. My emails to David on the subject were not returned. Even funnier, I was in Taiwan that week. Funny because my Taiwan friends accuse me of bringing earthquakes with me from California. As I blogged last year, I was in Taiwan for both the July 2009 and the September 1999 earthquakes, also typhoons and an airplane crash. Pure coincidence I assure you.

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Redefining the Semiconductor Foundry Model: Abu Dhabi versus Taiwan

Redefining the Semiconductor Foundry Model: Abu Dhabi versus Taiwan
by Daniel Nenni on 04-11-2010 at 2:53 pm
Categories: EDA, Foundries, GlobalFoundries, Siemens EDA, TSMC

It was a pleasure to see the GlobalFoundries (GFI) corporate pitch at the Mentor Graphics U2U Conference last week. Wally Rhines is a tough act to follow but Mojy Chian, Senior Vice President of Design Enablement at GlobalFoundries, presented a compelling argument for a refined foundry business model. The GFI people were also nice enough to send the presentation, offer a private briefing, and honor my request for a picture of an actual 28nm test chip wafer.

I first met Mojy Chian at Conexant and again at Altera where he was Vice President of Technology managing development, infrastructure, and manufacturing (down to TSMC 40nm). I last met Mojy at lunch on St Patrick’s day. When I heard Mojy joined GlobalFoundries I knew they were absolutely serious about the business side of semiconductor design and manufacturing.

Clearly the fabless model continues to thrive at 40nm and below. Due to the cost, only a handful of semiconductor manufacturers will develop 28nm process technology. Due to the cost, only the top fabless companies will design at 28nm, so the competition for their business will be fierce. The challenge for GlobalFoundries is to differentiate from Taiwan and that was the underlying message in this presentation: “GlobalFoundries is everything TSMC is not”.

Point #1 is the basis for their name, being global and not putting your semiconductor manufacturing eggs in one regional (Taiwan) basket. TSMC’s Morris Chang responded directly to this “Global Semiconductor Company” challenge by saying that TSMC will stay in Taiwan. The major reason being the economies of scale. According to Chang, TSMC only needs to run its Taiwan wafer fabrication plants at 40% capacity to break even, compared with 80% for “global” rivals.

The Chartered Semiconductor Common Platform marketing initiative will continue under GFI. In theory, the process development is collaborative and the cost is shared amongst the members. Common Platform clearly did not work for the now defunct Chartered Semiconductor which in my opinion was an implementation problem. If GFI drives this alliance hard it will work, believe it.

Point #2 is technology and the differing versions of HKMG technology. David Lammers did an excellent write-up: Gate First or Gate Last: Technologists Debate High-k . The bottom line is that Intel and TSMC will do Gate-Last. GFI, IBM, and other Common Platform Alliance members will do Gate-First. From what I have learned, Gate-Last will favor high performance and high yield designs but will require restricted design rules (RDRs). Gate-First will favor low power and smaller die sizes but may not scale past 22nm. I see this as a major battle ground for the foundry business. My opinion, whoever wins the 28nm node will lead the foundry business for the next decade.

Point #3 is semiconductor design enablement or the EDA, IP, and Design Services ecosystem. GlobalFoundries has Common Platform, TSMC has the Open Innovation Platform. One thing that has changed with Common Platform is that GFI is providing generous financial incentives for partners and we are talking about millions of dollars in life lines to companies that have struggled for profitability. GFI also pledged not to compete with partners, which is a direct shot at TSMC who has spent 100’s of millions of dollars developing proprietary design enablement technology.

Speaking of TSMC design enablement, the annual TSMC 2010 Technology Symposiums start next week in San Jose with Morris Chang as keynote speaker. TSMC has scheduled an in-person briefing for me with Shang Yi Chiang, senior vice president of R&D, to discuss 28nm technology so next week’s blog will be a follow-up to this.

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Redefining the Foundry Model: TSMC versus GlobalFoundries

Redefining the Foundry Model: TSMC versus GlobalFoundries
by Daniel Nenni on 04-10-2010 at 2:08 am
Categories: Foundries, GlobalFoundries, TSMC

The 17[SUP]th[/SUP] annual TSMC Technical Symposium finished its North American tour in Boston, a day before the Boston Marathon. I would like to be clever and say the foundry business is also a marathon but it clearly is not. If you watch TSMC, the foundry business is both a sprint AND a marathon!

In contrast to the previous blog on Global Foundries, the three key points to TSMC’s success are Leadership, Technology, and Experience. Rick Cassidy, President of TSMC North America, opened the symposiums with 30 slides of analogies and perspective featuring the US Olympic Bobsledding team.

Point #1 Leadership: Clearly TSMC is the leading foundry in all aspects of the business. The question is can TSMC continue in that role for another decade? I think the answer rests squarely on point #2.

Point #2 Technology: My 30 minute meeting with Dr. Shang-Yi Chiang, Vice President of TSMC R&D, should be a blog in itself but let me say here that he is one of the smartest, humble, and most believable men I have met. The big announcement Dr Chiang made was that TSMC would skip 22nm in favor of 20nm. My first question was why? Well, for two reasons (1) TSMC continues to see a 70% shrink as the optimum scaling factor: 40nm->28nm, 28nm->20nm, 20nm->14nm, 14nm-> 10nm. (2) Is my reason: Because TSMC can, and it gives them a competitive advantage. The predominate foundry business challenge is price cutting (2[SUP]nd[/SUP] and even 3[SUP]rd[/SUP] sourcing) so making your process as sticky as possible is the ultimate business goal. High volume designs will absolutely take advantage of the performance/power/area savings of a 20nm process versus 22nm. Look for the other foundries to follow suit as they did with 45 to 40nm in order to be competitive.

My second question for Dr Chiang was why Gate-Last versus Gate-First for 28nm? TSMC actually had parallel 28nm projects: Gate-First, Gate-Last, and Poly Gate. The winner was the Gate-Last 28nm implementation coupled with Restricted Design Rules due to scalability, performance, and yield. Dr Chang also stated that there is not an area penalty using RDRs which defies my personal experience with Recommend Design Rules.

My third question was about 40nm, what really happened with yield? Dr Chiang viewed it positively as a “learning” experience which resulted in technologies and practices that will enable 28nm and below (restricted design rules). TSMC saw 40nm designs with 4 billion + single VIAs, so VIA failure was an issue. Process variation was also a major issue, which I have blogged about before:

Moore’s Law and 28nm Yield
Moore’s Law and 40nm Yield


Dr Chaing did say that 40nm is “comfortably in production” at Fab 12 and 14. Expansion projects will double TSMC 40nm capacity by the end of the year. Giga Fabs like 12 and 14 can produce 100,000+ 12 inch wafers per month! Compared to Mini Fabs (10k+) and Mega Fabs (30k+). Capacity and the ability to satisfy the high volume needs of the top fabless semiconductor companies is key, believe it. He also said 28nm is on track with risk production in Q2 2010, which puts TSMC 6 months ahead of GlobalFoundries.

Point#3 Experience:TSMC also owns this one. IDM experience and Foundry experience are two very different things. One example is semiconductor IP and how it integrates into your design. Characterized, Modeled, Silicon proven IP from TSMC itself and TSMC early access partners like Virage Logic will ease integration issues and speed wafer sales. IP such as SRAM is used as pipe cleaners for new processes, which is why Virage was the first to announce products on TSMC 28nm. Other experience examples include silicon proven PDKs, Reference Design Kits and Flows.

This is my favorite Rick Cassidy slide, tight integration indeed:

My second favorite slide: mega fab costs are comparable to a Nimitz Class Aircraft carrier, minus the aircraft ($5B+). The question is, how many companies will be able to afford a fleet of aircraft carriers in the coming years, TSMC and?

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TSMC 2011 Forecast and 28nm Update!

TSMC 2011 Forecast and 28nm Update!
by Daniel Nenni on 03-31-2010 at 10:05 pm
Categories: Foundries, TSMC

My visit to Taiwan last week was very encouraging. No earthquake, no typhoon, and both TSMC and UMC again posted record financial results, giving a peek into what 2011 has in store for us semiconductor professionals around the world.

A transcript from the TSMC earnings call can be foundhere, the UMC transcript is here. The TSMC transcript is 19 pages long so let me save you some time with the key financial points:

  • TSMC’s net sales reached NT $412.3 billion ($13.4730 billion USD), up 6.9% from Q2 and up 24.8% from the same period a year ago.
  • Wafer shipments were 3.19 million 8 inch equivalent wafers, up 9% from the prior quarter and up 30.5% from the year ago quarter.
  • Operating margin was 38.4%, down 2% points sequentially, but up 2.8% points compared with year ago quarter.
  • EPS for Q3 reached NT$1.81, ROE was 36.5%.
  • Q3 gross margin was 50%, up by 0.5% points from 49.5 in Q2, mainly due to continued cost improvements.
  • Operating expense increased NT$1.6 billion from Q2, primarily due to a higher level of development activities for our 28 nanometer and 20 nanometer technologies, and also a higher opening expense for our Fab 12.
  • Ended Q3 with $5B+ USD in cash and short term investments


“Our mission is simply to be the technology and capacity provider of the global logic IP industry for years to come. We want to be the technology and capacity provider of the largest IP industry for years to come.”
Morris Chang was again on the conference call. Morris resumed as TSMC CEO June 2009 after passing the CEO baton to Rick Tsai in July 2005. I really am glad Morris is back at TSMC! According to Morris:

  • Q3 was a historical record in revenue dollars, in gross margin and in net income dollars.
  • If Q4 were at the same exchange rate at Q3, then Q4 guidance would be revenue NT$111.6 billion to NT$113.7. billion which is higher than Q3 actual.
  • Gross margin percentage would be 49.5% to 51.5%, which is also higher than the Q3 actual.
  • CAPEX will be $5.5 billion this year, CAPEX will be greater in 2011.
  • 71 customer 28 nm tape outs already scheduled.
  • We are forecasting total foundry revenue growth will be 14% in 2011.


One thing that Morris said that needs clarification is on 28nm portability:

I also wanted to point out that as the 28 nanometer generation, customer designs are very difficult to port between foundries. They’re very difficult to move from one foundry to another. This is a new phenomena that did not exist even in the 45-40 generation.

It is true that TSMC 28nm designs cannot be manufactured at other foundries with little or no modifications like 40nm. TSMC 28nm designs can however be migrated to other foundries using process migration tools from Sagantec. Magma and Cadence also have migration tools (Titan ALX and Virtuoso Layout Migrate) but they both have complexity and capacity issues. Process migration is only a $10M market so I doubt Magma or Cadence will put much more effort into it. I’m currently working on 28nm migration projects with Sagantec so I know this by experience.

Communications (mobile internet) will continue to drive semiconductors in 2011 and the rest of this decade. Smartphones give people access to information and information is power. In India and China even the poorest of poor people have mobile phones. No indoor plumbing, but everyone has a mobile phone. Access to information raises the aspirations of the poor which will in turn force governments to acknowledge poverty and do something about it. The semiconductor industry is changing the world, believe it.

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TSMC versus SAMSUNG

TSMC versus SAMSUNG
by Daniel Nenni on 03-07-2010 at 8:49 pm
Categories: Foundries, TSMC

According to the EETimes – “The leading-edge foundry market is up for grabs, as several vendors have stumbled or been victims of the shakeout “. According to people who actually work with the foundries, like myself, the leading edge foundry market will continue to be dominated by TSMC and GlobalFoundries is the “dark horse”. Samsung is now and will always be an IDM, with the foundry business being a diversion at best.

The EETimes also claims that TSMC “stumbled and had yield issues at the 40-nm node.”Again not true. TSMC has more than 80% of the 40nm market with 60+ products in production. TSMC forecasts 40nm accounting for 20% of overall revenues at the end of 2010, compared to 9% in the fourth quarter of 2009. Other foundries would be lucky to stumble into numbers like that!
TSMC Fab 12 is currently capable of producing 80,000 12-inch equivalent wafers on 40nm every quarter and will double that by the end of 2010. TSMC’s other 300-mm GigaFab, Fab 14, can also be used to meet future 40nm demand.
The widely reported TSMC 40nm yield problems were focused on GPUs. GPU products are bleeding edge technologies that drive process development, including half nodes. There are (5) GPU players withmarket share: Intel, Nvidia, AMD/ATI, S3, and SiS. Intel is an IDM, the rest manufacture at TSMC. Why TSMC you ask? Because GPUs are the single most difficult product to yield and TSMC is the only foundry that can accommodate the insanely competitive GPU market.

According to Ana Hunter, Samsung Semiconductor Vice President of Foundry Services, after 4+ years of trying “Samsung’s share of the foundry business is not as big as we want, but it takes time to put the pieces in place and ramp designs.”Prior to Samsung, Hunter spent 9+ years at Chartered Semiconductor, which was bought by GlobalFoundries last year for pennies on the invested dollar. Hunter stated that “The foundry business is part of our core strategy” and highlighted 6 reasons why Samsung believes it will succeed:

[LIST=1]

  • Capacity – Samsung plans to double its production of chips for outside customers every year until it rivals market leader TSMC. ( Wow, good luck with that!)
  • Resources – Samsung is one of the few companies that has the resources to compete at the high-end of the foundry market. (Intel, IBM, TSMC, GFI….)
  • Leading Edge Technology – Samsung is ramping 45-nm technology at a time when TSMC and others are struggling in the arena. (Oh no she di’int!)
  • Leading Edge Technology part II – Samsung will be one of the first foundries to roll out a high-k/metal-gate solution. The technology will be offered at the 32- and 28-nm nodes, which will be rolled out this year. (TSMC and GFI will go straight to 28nm HKT this year)
  • Leading Edge Technology part III – Unlike rival TSMC, Samsung is using a gate-first, high-k technology, TSMC is going with gate-last. We think that gate-first is best suited for today’s needs. (I defer to TSMC on this one, they have forgotten more about the foundry business than most will ever know.)
  • Ecosystem – Samsung has put the EDA pieces in place for the design-for-manufacturing puzzle. (A puzzle analogy, really?)
    Now let me highlight 6 reasons why I believe Samsung will not succeed:

    [LIST=1]

  • Business Model – The Foundry business is services centric, the IDM business is not. This is a serious paradigm shift for Samsung.
  • Customer Diversity – Supporting a handful of customers/products is a far cry from supporting the 100’s of customers and 1,000′s of products TSMC does.
  • Ecosystem – An open ecosystem is required which includes supporting commercial EDA, Semiconductor IP, and Design Services companies of all shapes and sizes.
  • Conflict of Interest – Pure-play foundries will not compete with customers, Not-pure-play foundries (Samsung) will. Would you share sensitive design, yield, and cost data with your competitor?
  • China – The Chinese market represents the single largest growth opportunity for the foundry business. TSMC has a fab in Shanghai and 10% control of SMIC (#4), UMC (#2) has control of China’s He Jian (#11), and Samsung does not even speak Mandarin.
  • Competition – The foundry business is ultra competitive, very sticky, and product dumping will not get you from #9 to #1.Just my opinion of course.
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TSMC vs GlobalFoundries vs IBM

TSMC vs GlobalFoundries vs IBM
by Daniel Nenni on 02-28-2010 at 10:22 pm
Categories: Foundries, GlobalFoundries, TSMC

Last week TSMC hosted the2010 Executive Forum on Leading Edge Semiconductor Technology in Yokohama, Japan. The Senior Vice President of R&D at TSMC lectured on process development and the individual technologies for the 45/40nm, 32/28nm and 22/20nm nodes and explained the current status.

Dr. Shang-Yi Chiang joined TSMC in July 1997 as Vice President of Research and Development (R&D). He temporarily retired from TSMC as Senior Vice President of R&D in July 2006 and returned in September 2009 to resume this position.

Dr. Chiang, a fellow of IEEE, received his Bachelor of Science degree from National Taiwan University in 1968, his Master of Science degree from Princeton University in 1970, and his Doctorate from Stanford University in 1974, all in electrical engineering. In 2001, Dr. Chiang was chosen as one of the 50 “Stars of Asia” by BusinessWeek Magazine. This award recognizes the outstanding performance of TSMC’s R&D team under Dr. Chiang’s leadership, and his vision and strategies for continued aggressive R&D development despite the industry-wide downturn.

The new technologies introduced for the 45/40nm process include ArF immersion exposure, the third-generation strained silicon and a low-k interlayer insulating film whose dielectric constant was lowered to 2.5. Though TSMC had chamber matching and ion implanting problems for the 45/40nm process, it has solved the problems and is now rapidly ramping the technology. The number of tape-outs have increased at a rapid rate, and half of the taped-out chips are now being mass-produced, TSMC said.

The most important new technology for the 32/28nm process is a new gate. A SiON gate insulating film is used for the low-power type (28LP) while a high-dielectric gate insulating film and a metal gate electrode (high-k/metal gate) are used for the high-performance type (28HP) and the medium-speed, low-leakage type (28HPL).

As a process to form the high-k/metal gate, TSMC employed the gate-gate-last process instead of the gate-first process, which the company was planning to use at first. Also, it will introduce the fourth-generation strained silicon and low-resistance Cu wiring. TSMC lowered the resistance of Cu wiring by improving the flatness of the boundary surfaces of the Cu and barrier metal to prevent electrons flowing on the surface of the wiring from scattering.

Besides TSMC, IBM and GLOBALFOUNDRIES have initiated research projects to enable the scaling of semiconductor components to the 22 nanometer node and beyond. Back in June 2009, GlobalFoundries described an innovative technology that could overcome one of the key hurdles to advancing high-k metal gate (HKMG) transistors, enabling the next generation of mobile devices with more computing power and improved battery life.
An interesting race indeed, the prize being the top foundry customers around the world: Qualcomm, Broadcom, Xilinx, Altera, AMD/ATI, Nvidia, Apple, etc…

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TSMC 28nm Design Advisory

TSMC 28nm Design Advisory
by Daniel Nenni on 01-31-2010 at 11:49 pm
Categories: Foundries, TSMC

Transistors may be shrinking but atoms are not. Transistors are now just a handful of atoms so it matters even more when a couple of those atoms are out of place. Process variations, whether they are statistical, proximity, or otherwise, have got to be thoughtfully accounted for if we are to achieve the low-power, high-performance, and high yield design goals at 28nm.

A recent seminar byTSMC and Synopsys entitled “32/28nm Challenges – The EDA Vendor and Foundry Perspective” brought perspective to the coming design challenges. The TSMC section presented by Tom Quan is well worth seeing. Tom Quan has 30 years design and product development experience in the AMS market space. You won’t find a more engaging speaker on process variation than Tom Quan.

TSMC’s value proposition for moving to the 28nm process supports Moore’s Law with a better than 2X gate density at 28nm versus 40nm, a significant speed gain, plus reduced power leakage and an overall cost reduction. Target applications for 28nm include high performance computing and peripherals, low power devices such as HD video cameras, mobile internet and mobile computing, home and portable entertainment. TSMC’s Advanced Technology Roadmap is on track for the low power 28nm process in Q210 and high performance-high K metal gate 28nm process in Q310.

Tom Quan’s emphasis on the importance of “Variation-Aware Design” is justified. To start with, a smaller manufacturing window with much less margin to begin with equals more variation. Add to that the fact that global variation is constant, but local variation increases significantly as channel width and length decreases, and you will have a requirement for variation-aware design tools prior to GDS.
The overall TSMC design ecosystem emphasis is on collaboration between design and process. Tom divided this responsibility into Foundry: better SPICE accuracy, DFM rules, providing variation aware reference design kits (RDKs), and restricted design rules (RDRs). Designers: must be aware of layout effects, analyze-fix variation-aware methodologies will be required for area-yield tradeoffs, and pre- vs. post-layout simulation accuracy. The clear implication is that designers need to change their mindset in adopting a variation-aware design methodology as a requirement versus a luxury.

The conclusions are obvious. Partnerships between the foundry, EDA and SemIP providers, and customers will be required to eliminate silicon waste at 28nm. Partnerships that are friendly and cost effective, with shared responsibility will result in productive and innovative solutions to even the most technologically advanced challenges.

I’ve covered semiconductor process variation in my blogs on TSMC Process Variation, TSMC 40nm Yield Explained, Moore’s Law and 40nm Yield, and most recently Moore’s Law and 28nm Yield. I also work on process variation with the foundries and top semiconductor companies through strategic relationships with Solido Design Automation. Device sensitivity and process variability is something you will have to carefully model and design to at 28nm so be sure and look for variation aware methodologies before you start.

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TSMC versus Global Foundries Part II

TSMC versus Global Foundries Part II
by Daniel Nenni on 01-17-2010 at 11:52 am
Categories: Foundries, GlobalFoundries, TSMC

The foundry business is a tough one. The golden age of semiconductors is clearly over and what remains is a highly competitive marketplace. This blog follows up my original TSMC vs Global Foundries which is the single most viewed page on my site.

Case in point #1: Founded in 2000, SMIC Semiconductor Manufacturing International Corporation is billed as one of the leading semiconductor foundries in the world and the largest and most advanced foundry in Mainland China. Harvard Business School even wrote a case study on SMIC’s business model, characterized as a Reverse Build-Operate-Transfer (BOT). Unfortunately cheap labor does not a foundry make. It takes highly experienced workers, advanced manufacturing technology, strategic marketing, and an ultra competitive business model. The semiconductor foundry business is a marathon, not a sprint. Also see TSMC vs SMIC.

Case in point #2: Chartered Semiconductor was created in 1987 as one of the world’s dedicated semiconductor foundries. Chartered Semiconductor continued a string of losing quarters until the Abu Dhabi government-owned Advanced Technology Investment Company (ATIC) acquisition was passed by investors in a majority vote. Shareholders bought Chartered shares at the 1999 initial public offering (IPO) price of S$3.34, the shares were later consolidated at 10 for 1, so they effectively cost S$33.40 each. ATIC paid S$2.68 a share. Chartered had experienced workers and strategic marketing (Common Platform), but lacked the advanced manufacturing technology and competitive business model to be successful.
2010 brings us a truly global foundry with the ATIC acquisitions of the manufacturing arm of AMD and Chartered Semiconductor. Global Foundries now employs 10,000+ people spanning 3 continents and 12 locations with manufacturing operations in Singapore, Dresden, Germany, and a new leading-edge fab under construction in Saratoga County, New York. Global Foundries was founded with $4.5 billion in cash, with future backing going up to $7B. The New York fab alone will cost an estimated $4.5B.

GFI now has about $3B in revenues from more than 150 customers that include many of the world’s top fabless and fab-lite companies, such as AMD, Qualcomm, STMicro, IBM, and Toshiba. Process geometries in production are: .5um, .35um, .25um, .13um, .18um, 90nm, 65nm, and 45/40nm. Process geometries in planning are: 32/28nm and 22/20nm. Planned capacity is 1.6 million 300mm wafers annually by 2014, supplemented by 2.2 million 200mm wafers a year. Global Foundries has highly experienced workers from Chartered Semiconductor and AMD, cutting edge manufacturing technology from AMD and IBM, strategic marketing from Common Platform, add in a competitive business model and you will have the #2 foundry in the world.

In comparison TSMC has 23,000+ employees and will add 3,000 more in 2010. With $10B+ in annual revenues, TSMC accounts for 50% of the foundry market revenue and 80% of the profits. TSMC is considered a first source for semiconductor manufacture, meaning that leading fabless semiconductor companies work with TSMC first, then replicate manufacturing at the other foundries for redundancy and cost reductions. Global Foundries will challenge TSMC for first sourcing with AMD manufacturing technology and a manufacturing process partnership with IBM. In fact the first production 28nm wafers by a foundry were displayed by GFI at the Consumer Electronics show in Las Vegas this month. At least one of the wafers contained AMD/ATI GPUs.

Unfortunately the semiconductor foundry market is a maturing industry and likely to experience single digit annual growth in coming years. To diversify, TSMC is investing heavily in solar power and light-emitting diodes. Both are fast growing markets, have technological overlap with chip production, and offer far better margins and upside potential. There is a reason why TSMC is the #1 foundry in the world and I don’t see that changing anytime soon. But competition breeds innovation so the foundry business will be much more interesting to watch with GFI challenging TSMC.

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TSMC Yields @ 28nm!

TSMC Yields @ 28nm!
by Daniel Nenni on 12-31-2009 at 8:00 pm
Categories: Foundries, TSMC


It was an interesting week in Taiwan for sure. Typhoon Fanapi, lightning storms, the first 28nm production silicon, foundry re-orgs, and most importantly Moon Cake pastries! Wednesday was the Chinese Moon (Zhongqiu)Festival, in Taiwan it is a National holiday commonly celebrated by people barbecuing various meats outdoors. I just love those moon cakes!

The biggest news is that Altera demonstrated production silicon @ TSMC 28nm for the Stratix V FPGA family, originally unveiled in April of this year. Altera is using the HP (high performance) version of TSMC 28nm, the same process that the GPU vendors use, so expect TSMC 28nm production silicon announcements from Nvidia and AMD/ATI in the next quarter or so. Altera was the first to yield on TSMC 40nm so they clearly know what they are doing. Xilinx will also use TSMC 28nm, expect an announcement this week.

Speaking of Nvidia, CEO Jen-Hsun Huang did a candid interview on the technical difficulties of the TSMC 40nm Fermi chip:

“The parasitic characterization from our foundries and the tools and reality are simply not related, at all. We found a major breakdown between the models, the tools, and reality.”

You can interpret this different ways and the press certainly will. Enlightened semiconductor people know however that process models evolve while processes ramp. Early access companies such as Nvidia, Altera, AMD/ATI, Qualcomm, etc… start designs with pre production process models. The amount of changes to the models varies but 40nm broke revision records for sure. I have seen this many times while working with early access IP companies.

As I blogged in:

  • Moore’s Law and 40nm Yield
  • TSMC 40nm Yield Explained
  • EDA Marketing Fail TSMC Process Variation

Process variation really kicked in at 40nm and those that prepared yielded, those that didn’t, didn’t, simple as that. The process models had variation built into them but the main stream EDA tools did not. So Jen-Hsun was right, there was a major breakdown between the models and the tools. The reality breakdown however was a design management issue within Nvidia, which Jen-Hsun acknowledged in the interview.
The other news from Taiwan is the departures of Fu-Cheih Hsu and S.T. Juang from the TSMC Design and Technology Platform unit, founders of the TSMC Open Innovation Platform (OIP). EETimes broke the story on 9/20/2010 with “TSMC’s Design Guru Resigns”. Fu-Cheih actually left in August (typical mainstream media lag) with S.T. Juang following him in September.

I’ve received a lot of emails on this from vendors and customers alike. The big question is: will the TSMC OIP initiative continue? The answer of course is: YES it will. Fu-Cheih’s replacement is Cliff Hou who is even more qualified to advance the OIP agenda. Cliff is much more approachable, easy to work with, and has more “hands-on” semiconductor design enablement experience.

Cliff joined TSMC in Dec 1997 as a section manager responsible for process design kit (PDK) and reference flow development from 0.35m to 65nm. In 2007 Cliff became senior director of TSMC in-house IP development. TSMC IP includes: standard cells, IO’s, embedded memory compilers, analog blocks, and high-speed interface modules. He has a B.S. degree from National Chiao-Tung University, and a Ph.D. from Syracuse University, New York. He is also a member of the board of directors of Global Unichip Corp. Cliff knows semiconductor design enablement, absolutely.

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TSMC Open Innovation Platform Explained

TSMC Open Innovation Platform Explained
by Daniel Nenni on 11-09-2009 at 10:56 pm
Categories: Foundries, TSMC

Launched in April 2008, the TSMC Open Innovation Platform initiative is a collaborative strategy aimed at breaking the bottlenecks of semiconductor design enablement in order to promote growth for the industry as a whole. The TSMC iPDK Debate: Lets Play Monopoly! blog I did provides more technical detail.

While Wafer count is climbing, an estimated 20M in 2009 to 30M in 2013, semiconductor design enablement (includes Electronic Design Automation-EDA, Semiconductor Intellectual Property-IP, and Design Services-DS) will continue to stagnate and consolidate.

The main reason for the disjointed wafer count increase and design enablement revenue stalling is FPGAs. As programmable devices advance in speed and density, medium-to-small volume projects and emerging technology companies will continue to leverage the low barrier to entry of FPGAs. Wafer count climbs from FPGA vendors such as Xilinx, Altera, and Actel, while ASIC design starts decline.
Other reasons for the ASIC design start decline include:

  • High cost, it takes $50-70M to get an ASIC to market.
  • Increased SOC design density and complexity, the chips are bigger so there are less of them and require many more resources to complete.
  • High mortality rate, an estimated 50% of the ASIC design starts do not make it into production.
  • Less ASIC design starts equals less design experience, less design experience equals higher ASIC mortality rate.


The TSMC Open Innovation Platform promotes timeliness-driven innovation amongst the semiconductor design community, its ecosystem partners and TSMC’s IP, design implementation and DFM capabilities, process technology and backend services. The Open Innovation Platform™ includes a set of ecosystem interfaces and collaborative components initiated and supported by TSMC that efficiently empowers innovation throughout the supply chain and enables the creation and sharing of newly created revenue and profitability. TSMC’s AAA initiative is a critical part of the Open Innovation Platform™, providing the accuracy and quality required by ecosystem interfaces and collaborative components.

The financial goal of OIP is obvious, to reduce waste in the semiconductor design enablement supply chain. People in this industry are accustomed to waste, business as usual, so this is a significant challenge! Jack Harding of eSilicon estimates a 20% waste due to inefficiencies and lack of experience. I say it is closer to 30% if you include the ASIC mortality rate. 20-30% of $50-70M is a significant amount, especially if you are asking a VC for it.

The TSMC OIP targets include the following areas of inefficiencies:

  • PDKs, the iPDK standard is innovation driven versus format driven, which reduces foundry and customer support costs.
  • EDA Reference Flows and tool qualification, verified design sign-off flows reduce both costs and customer learning curves.
  • TSMC IP portal, documenting silicon proven IP from both TSMC and commercial IP vendors such as Virage Logic. Cross distribution deals are also possible.
  • TSMC collaborated services, such as Tela Innovations Power and Area Trim.


The bottom line is that to increase ASIC design starts we must decrease the barrier to entry, we must reduce risk, we must all focus on success based business models:

  • TSMC is certainly success based with wafer pricing but must look at reducing NRE (mask costs) which are in the millions of dollars.
  • IP companies are success based capable with foundry sponsored IP (free to customers), and royalty based IP, but there are still significant up-front licensing fees for leading edge products.
  • Design Services (eSilicon) are definitely success based with per chip pricing for working silicon.
  • EDA is still in the dark ages with yearly subscriptions or all-you-can eat product dump pricing where you pay whether you use it or not, whether you are successful or not.

This was the second OIP conference, it was stocked with executives from TSMC and the design enablement food chain. The keynotes, panels, and discussions were highly interactive, the format and content is exactly what our industry needs to scale and move forward in a profitable manner.