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How Apple Plans to Leverage Intel’s Foundry

How Apple Plans to Leverage Intel’s Foundry
by Ed McKernan on 12-09-2012 at 4:00 pm
Categories: Arm, Foundries, Intel Foundry, TSMC

Tim Cook’s strategy to disengage from Samsung as a supplier of LCDs, memory and processors while simultaneously creating a worldwide supply chain from the remnants of former leaders like Sharp, Elpida, Toshiba and soon Intel is remarkable in its scope and breadth. By 2014, Apple should have in place a supply chain for 500M iOS devices (iPhones, iPADs, iTVs and iPODs). Add in the near term foundry relationship with TSMC and it spells not just freedom but a true Vertical Operations independent from its number 1 competitor. Add to this the fact that Apple may soon be lower in cost, an inconceivable thought to most observers. How can Apple have lower cost than Samsung? This is the story of 2013-2014 as Tim Cook is attempting to put the last pieces in place to build affordable $200 iPhones and $250 iPAD Minis for the other half of the world that is currently unaddressed today (eg China Mobile and India).

A recent article in digitimes questions whether TSMC will have enough capacity to support Apple’s projected demand of 200MU while also servicing its other major customers like Qualcomm, Broadcom, nVidia and the rest of the leading edge silicon buyers. Will TSMC make the investment to capture all of mobile while Intel sits on three empty 14nm fabs? Not likely, unless Apple and Qualcomm write checks to guarantee the demand. Six months ago Qualcomm started down the path of diversification when demand skyrocketed and TSMC could not turn on a dime to fulfill. Tim Cook knows Jony Ive will continue to pump out great products at a more rapid pace in the coming quarters and try to deny Samsung and Microsoft an opening like in the past during summer lulls when yearly refreshes were still waiting in the wings. All that is holding Apple back is the global supply chain that is larger and lower cost than what Samsung has today.

Many in the press have spent the past 6 months talking about the transition taking place from Samsung to TSMC. They have overlooked how Apple is leveraging its Japan infrastructure to build LCDs, DRAM and NAND Flash at a time when the Yen is about to collapse. From the mid 1980s to today the Yen has appreciated by 300% relative to the dollar. Moore’s Law is a hugely deflationary force that requires a country to offset its Creative Destruction by inflating away its currency. So the US and half the world linked to the Dollar (including China) have prospered while the Japanese economy has contracted during these past 25 years. If the Yen drops dramatically from 80 to 120 or 150, as is necessary to restart their economy, then Apple will have the beginnings to its low cost strategy to outflank Samsung. A robust, high volume processor and baseband chip supply chain is all that remains.

When the Intel earnings call comes in January, I anticipate a number of analysts will demand a full accounting of the projected fab loadings for 22 and 14nm for 2013 and 2014. The timing of recent leaks on Intel and Apple negotiating a Fab deal is not unexpected. On the table are three 14nm Fabs that require no Apple capital investment to satisfy the demand beyond the 200MU that TSMC and Samsung can supply. Quite likely Apple has the opportunity to support more than 500MU additional units with Intel at current die sizes. But wait, Apple will get an extra shrink and significantly lower power in a move to Intel’s 14nm process. Therefore the Intel Fab option is really the one road available that catapult Apple beyond Samsung in their battle for market share leadership in Smartphones and Tablets. It is also the one option that is unavailable to Samsung.

Analyst Doug Freedman recently speculated that Intel and Apple are considering a Foundry partnership where the former agrees to build ARM chips for the iPhone while the latter will convert the iPAD to x86. It’s possible, but in the end I believe that three empty Fabs running 14nm Finfet is a much stronger religion than x86 architected chips. Intel would be happy with anything Apple wants built because there are tremendous sunk costs in place with the new fabs. This is where TSMC has to be cautious.

While Stacy Smith, Intel’s CFO, repeated at a conference last week that they don’t see PC volume falling again in 2013, there are hints that Ivy Bridge pricing has already been reduced to move the ultrabook price points down to sub $500. Smith also noted that 22nm Fab equipment is now being transitioned into 14nm fabs. The Ireland Fab may be on hold now, but in reality it is like an Aircraft Carrier waiting to be outfitted with Fighters. Six large Fabs are what await the combined x86 and Apple demand. Of the six, less than three are currently needed to support 350M PCs and 20M-x86 based Servers. Any slide in x86 demand just opens up more space for Apple and at lower prices.

At some point the operating margins building the A7 for Apple will cross above those of an Atom chip. Just to be clear, I am saying that an A7 will deliver more profit than an Atom chip when Sales, Marketing and Engineering costs are factored in for the latter. If Intel can sell Apple on its 4G LTE baseband, then the low cost, dual sourced processor and baseband supply chain will be complete.

Scenarios such as those above are only possible when markets are going through huge transitions. I am still intrigued by Intel’s decision to double its fab footprint back in 2010. What were the reasons for the boldness and is that view today still held internally. I can only speculate that they truly believed that they alone would get to 14nm while the rest of the industry faded.

Full Disclosure: I am Long AAPL, INTC, ALTR, QCOM

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Is The Fabless Semiconductor Ecosystem at Risk?

Is The Fabless Semiconductor Ecosystem at Risk?
by Daniel Nenni on 11-18-2012 at 6:00 pm
Categories: Events, Foundries, Intel Foundry, TSMC

Ever since the failed Intel PR stunt where Mark Bohr suggested that the fabless semiconductor ecosystem was collapsing I have been researching and writing about it. The results will be a book co-authored by Paul McLellan. You may have noticed the “Brief History of” blogs on SemiWiki which basically outline the book. If not, start with “A Brief History of Semiconductors”. In finding the strengths of the fabless semiconductor ecosystem I also discovered possible weaknesses.

Deep collaboration with partners and customers is the current mantra we hear at every conference. TSMC even spelled it out at the most recent OIP Forum last month: At 40nm partners and customers started design work when the PDK was release 0.5, at 28nm design work started at PDK 0.1, at 20nm design work started at PDK .05, and 16nm will start at PDK .01. The problem with this is that the earlier the collaboration the more sensitive the data is and this data is being shared with partners and customers who also work with competing foundries. It is a double edged sword and the cause of unnecessary bloodshed in our industry.

The only protection this sensitive data has is the NDA (Non Disclosure Agreement) which ranks right up there with toilet paper in our industry. One of the things I do as a consultant for emerging fabless, EDA and IP companies is help with NDAs. My least favorite is the 3-way NDA where the customer, the EDA vendor, and the foundry all have to sign it. How do you control that information flow?

NDAs have evolved over the years and the recent ones are much more detailed and have some serious legal repercussions but who actually reads them besides me and the lawyers?

The problem is that the EDA industry is very small and we all know each other. Industry people regularly gather at local pubs, coffee houses, and conferences and things tend to slip out. There is also an EDA gossip website that has no respect for sensitive data covered under NDAs.

So you have to ask yourself what is a foundry to do? How do you allow early access to your secret recipes without it being leaked to your competitors? Just some ideas:

Buy an EDA company: I suggested to GLOBALFOUNDRIES in the early days that they tap their oil reserves and buy Cadence. Imagine the seamless tool flow a foundry could create today if they had full control of the tools and information flow. Also imagine the fabless semiconductor industry growth potential if EDA tools were free, like FPGAs, design starts would multiply like bunny rabbits!

Limit the number of EDA companies you do business with:This is my personal nightmare. To cut costs and increase security a foundry would only work closely with the top 2 EDA companies. Granted this would kill emerging EDA companies and stunt the growth and innovation of EDA but it could happen. It would also increase the costs of EDA tools thus killing design starts.

Legal training for all semiconductor ecosystem employees: Use the recent insider trading case law. People are doing serious jail time for leaking Intel, AMD, and Apple financial information. Spend the time to educate your employees on NDAs and focus on controlling the information flow. A couple of hours of prevention could prevent years of incarceration.

If you have other ideas lets discuss it here and I will make sure it is read by the keepers of the secret semiconductor recipes. We have some serious challenges ahead that will require even deeper collaboration so lets be proactive and protect the industry that feeds us.

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TSMC Financial Update Q4 2012!

TSMC Financial Update Q4 2012!
by Daniel Nenni on 11-11-2012 at 4:00 pm
Categories: Foundries, TSMC

The weather in Taiwan last week was very nice, not too hot but certainly not cold. The same could be said for the TSM stock which broke $16 after the October financial report where TSMC reported a sales increase of 15% over September. Revenues for this year thus far increased 19% over last year so why isn’t TSM stock at $20 like I predicted earlier this year?

I blame the Q4 and Q1 Fear, Uncertainty, and Doubt (FUD) everyone is talking about. I blame the “US Fiscal Cliff” everyone is writing about, it even has a wiki page! I was asked by politicians if my family was better off now versus four years ago and the answer is YES, absolutely! Why? Because money is cheap, the interest rate on my debt is less than half, and because I continue to invest in the future.

TSMC has done the same thing. TSMC has spent a record amount this year on CAPEX and R&D and it shows. 28-nanometer revenue and shipments more than doubled during Q3 2012 and total 28nm wafer revenue increased from 7% in Q2 to 13%. Expect 28nm revenue to exceed 20% of total wafer revenue in Q4 and will be more than 10% for the whole year.

TSMC 28nm capacity increased 5% to 3.8 million wafers in Q3 and was fully utilized. As Co-Chief Operating Officer Dr. Shang-Yi Chiang said at ARM TechCon last month, “The biggest 28nm challenge was forecasting with demand for 28nm this year being 2-3x of what was forecast.”

Congratulations to everyone on the success of 28nm TSMC. Teamwork, patience, and investment wins again! Let us not forget the “28nm does not work” FUD at the beginning of the year. As I predicted 28nm will be the best process node we will see for years to come, believe it. Since the other foundries are still struggling with it, I predict 28nm will be the most successful node in the history of TSMC. 28nm may even get a chapter in the book Paul McLellan and I are writing, if not a full chapter, certainly an honorable mention.

Back to the fiscal cliff – what will I do in the next four years? I will continue to invest but also pay down my debt. I did support President Obama for a second term and I strongly suggest he do the same, invest and pay down the National Debt. I offer the same advice to TSMC, continue to invest and the fabless semiconductor ecosystem will have another great four years!

Last quarter TSMC invested $1B in ASML for EUV and 450mm technology. TSMC also bought 35 acres of land in Zuhan (near Hsinchu Science Park) for another GigaFab research and manufacturing facility that will produce 450mm wafers starting at 7nm. TSMC 2013 CAPEX and R&D is expected to be “in the same ball park” as 2012, of course that all depends on 20nm and 16nm FinFETS and how accurate the 2013 forecast is. My guess is that TSMC 2013 revenue will beat 2012 by single digits and, due to the cost of 20nm and 16nm, CAPEX and R&D will also grow by single digits.

Remember, I’m not an analyst, journalist, or financial expert, I’m just a blogger who drives a Porsche.

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ARM adopting SpyGlass IP Kit, joining TSMC’s soft IP9000 Quality Assessment Program

ARM adopting SpyGlass IP Kit, joining TSMC’s soft IP9000 Quality Assessment Program
by Eric Esteve on 11-07-2012 at 12:17 pm
Categories: EDA, Foundries, TSMC

More than one year old now, TSMC’s soft IP quality assessment program is a joint effort between TSMC and Atrenta to deploy a series of SpyGlass checks that create detailed reports of the completeness and robustness of soft IP. This soft IP quality program has been the first to be initiated by a Silicon foundry on other than “Hard IP”, and is demonstrating how IP support, whether hard or soft, is important in TSMC strategy to best support their customers and shorten the design to Silicon delay and reduce the TTM. Currently, over 15 soft IP suppliers have been qualified through the program, including ARM, as recently announced by TSMC at ARM TechCon.

How does the flow works? Atrenta’s SpyGlass® platform provides a powerful combination of proven design analysis tools with broad applicability throughout the SoC flow. The SpyGlass platform includes a tool suite for linting, CDC verification, DFT, constraints analysis, routing congestion analysis and power management applicable at RTL as well as the gate level. Providing visibility to design risks early and at high design abstractions, SpyGlass enables Early Design Closure® –During the course of chip development, design goals evolve and get refined from the initial RTL development phase to the final SoC implementation phase. The SpyGlass platform offers a consistent solution that can be used effectively at each stage of the design process to achieve the respective design goals. The use of the right SpyGlass tools at the right stage of design development helps design teams achieve a predictable repeatable methodology.

The list of design goals addressed by GuideWare, a set of pre-packaged methodologies for SpyGlass, show that the risk of failure is early addressed, and can be minimized:

  • Will the design simulate correctly?
  • Are clocks and resets defined correctly?
  • Will the design synthesize correctly? Are there unintended latches or combo loops?
  • Will gate simulations match RTL simulations?
  • What will the test coverage be?
  • What is the power consumption of a given block?
  • What is the profile of this IP? (For example, gates, flops, latches, RAMS/ROMS, I/Os, tristates, clocks)
  • Are there any inherent risks or non-standard design practices used in this IP?
  • Are there any adaptation issues in the target SoC, such as power, routability or congestion?
  • Are all the incoming blocks truly ready for integration? Are they clean in terms of clocks/resets and constraints?
  • What are possible inter-block issues? (For example, are block-level constraints complete and coherent with target SoC constraints?)
  • What are “common-plane” issues among heterogeneous blocks? (For example, scan chain management and test blockages at the SoC level)
  • Can I leverage my block-level work (waivers, constraints) at the SoC level?

Coming back to TSMC soft IP quality assessment program, we can see that the list of IP partners is a who’s who including from Network-on-Chip IP vendor Arteris, DSP IP core supplier CEVA, PCI Express IP core (PLDA), configurable CPU IP core (Tensilica) to GPU and CPU IP core vendors with ARM Ltd. and Imagination Technologies, Video and Display IP (Chips and Media), and scanning also Dolphin Integration, Cosmic Circuits or GlobalUniChip, provider of mixed-signal IP. That’s really make sense that ARM, the #1 IP vendor, join this program, as well as it would really makes sense that at least two of the top 3 EDA & IP vendor, Cadence and Synopsys, would join the program, sooner or later…

Eric Esteve from IPNEST

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16nm FinFET versus 20nm Planar!

16nm FinFET versus 20nm Planar!
by Daniel Nenni on 11-04-2012 at 8:10 pm
Categories: FinFET, Foundries, TSMC

The common theme amongst semiconductor ecosystem conferences this year is FinFETS, probably the most exciting technology we will see this decade. A lot has been written on SemiWiki about FinFETS, it is one of the top trending search terms, but there is some confusion about the process naming so let me attempt to explain.

In planar process technologies the 28nm or 20nm implies the minimum transistor gate length of 28nm or 20nm. Corresponding to that lithographic capability are two other critical dimensions: the “contacted gate pitch” and the “metal pitch” for the lowest, thinnest metal layers. (Higher metal layers will be thicker with less resistance which are more suitable for longer routes but will have a greater width+space design pitch.)

Given that, the 16nm FinFET process technology is a bit of a misnomer. It was probably named by Marketing people to imply that the resulting performance when transitioning from planar to FinFET in a 20nm lithography process would be “between 20nm planar and 14nm FinFET”.

Why 16nm FinFETS you ask? Two reasons: (1) EUV is late so a true 14nm FinFET process will not be possible by 2015 and (2) Customers designing mobile devices were not willing to wait for the power savings FinFETS have to offer. As a result, the current 20nm lithography process was modified for FinFETs, and the 16nm FinFET process was born.

If you were to ask, “What is the minimum gate length, contacted gate pitch and metal pitch for 16nm FF, and how does that differ from 20nm SoC?”, you would get the answer that it’s the same litho design rules, just a different transistor structure.

There is one additional measurement that is introduced in a FinFET technology: the effective device width per micron. These are transistor parameters, and they are an indicator of performance, but they are relatively independent of the contacted gate pitch + metal pitch, which define the achievable circuit density.

The IBM 14nm FinFET tape out briefing provided some interesting process details. Disclosing this type of information is certainly not IBM-like so the stakes are obviously high in the race to FinFETs:

[TABLE] align=”left” style=”width: 470px”
|-
|
| 32nm
| 28nm
| 20nm
| 14nm
|-
| Architecture
| Planar
| Planar
| Planar
| FinFET
|-
| Contacted poly pitch
| 126nm
| 114nm
| 90nm
| 80nm
|-
| Metal pitch
| 100nm
| 90nm
| 64nm
| 64nm
|-
| Local interconnect
| No
| No
| Yes
| Yes
|-
| Self-aligned contact
| No
| No
| No
| No
|-
| Strain engineering
| Yes
| Yes
| Yes
| Yes
|-
| Double patterning
| No
| No
| Yes
| Yes
|-

Bottom line, lithographically, both 16nm and 14nm FinFET processes are still effectively offering a 20nm technology with double-patterning of lower-level metals and no triple or quad patterning.

One team has chosen to define the performance of their FinFET as a “half node” improvement (e.g., 20nm ->16nm), whereas the other has chosen to represent the performance of their FinFET as equivalent to a “full-node shrink” (20nm -> 14nm). There will be slightly different fin_height, fin_thickness, and fin_pitch parameters between the two processes but the circuit density is really still the same as 20nm.

Some designs might be smaller but in general I think FinFets at 16nm and 14nm will offer significantly lower power consumption and leakage but only marginally better performance and area than 20nm planar, just my opinion of course.

Who do you think will be first to get FinFETS into volume production? Would it be TSMC, Samsung, or GF? Check out the SemiWiki FinFET poll HERE. Anybody can vote so please do.

Also see:

GLOBALFOUNDRIES 14nm FAQ

FinFET Wiki

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Chip On Wafer On Substrate (CoWoS)

Chip On Wafer On Substrate (CoWoS)
by Daniel Payne on 11-03-2012 at 5:19 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

tsmc cowos test vehicle1

Our EDA industry loves three letter acronyms so credit the same industry for creating a five letter acronym CoWoS. Two weeks ago TSMC announced tape-out of their first CoWoS test chip integrating with JEDEC Wide I/O mobile DRAM interface, making me interested enough to read more about it. At the recent TSMC Open Innovation Platform there was a presentation from John Park, Methodology Architect at Mentor Graphics called –A Platform for the CoWoS Reference Flow. Continue reading “Chip On Wafer On Substrate (CoWoS)”

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SpyGlass IP Kit 2.0

SpyGlass IP Kit 2.0
by Paul McLellan on 11-01-2012 at 6:00 pm
Categories: EDA, Foundries, TSMC

On Halloween, Atrenta and TSMC announced the availability of SpyGlass IP Kit 2.0. IP Kit is a fundamental element of TSMC’s soft IP9000 Quality Assessment program that assesses the robustness and completeness of soft (synthesizable) IP.

IP Kit 2.0 will be fully supported on TSMC-Online and available to all TSMC’s soft IP alliance partners on Nov. 20, 2012, just in time to make sure your turkey is SpyGlass Clean.

TSMC’s soft IP quality assessment program is a joint effort between TSMC and Atrenta to deploy a series of SpyGlass checks that create detailed reports of the completeness and robustness of soft IP. Currently, over 15 soft IP suppliers have been qualified through the program. IP Kit 2.0 represents an enhanced set of checks that adds physical implementation data (e.g., area, timing and congestion) and advanced formal lint checks (e.g., X-assignment, dead code detection). IP Kit 2.0 also allows easier integration into the end user’s design flow and enhanced IP packaging options.

On the same subject, IPExtreme had an all day meeting at the computer history museum about, duh, IP. One of the companies presenting was Atrenta and here is a video of Michael Johnson’s presentation on IP Kit.

And, completely off topic, at the end of the IPExreme event they served wine and beer and had a short presentation on each beforehand. Jessamine McLellan, then the sommelier at Chez TJ in Mountain View (now the bar manager at the not-yet-open Hakkasan in San Francisco) gave a presentation on pairing wine with food. That last name sounds a little familiar…

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TSMC OIP Forum 2012 Trip Report!

TSMC OIP Forum 2012 Trip Report!
by Daniel Nenni on 10-21-2012 at 6:00 pm
Categories: EDA, Foundries, TSMC

The second annual TSMC Open Integration Platform Ecosystem Forum was last week and let me tell you it was excellent. Great update on the TSMC process technology road maps, great for networking within the fabless semiconductor ecosystem, great for seeing what’s new in EDA and IP, and great for SemiWiki. It was time well spent for sure. You can see my TSMC OIP 2011 trip report HERE for reference.


The opening video was excellent this year! It was all about collaboration of course and an orchestra is a perfect example. My wife played first chair violin so this theme really clicked with me. Last year’s theme was a rowing team which did not click with me. You can see the symphony videoHERE.

First up was Rick Cassidy. Rick is President of TSMC North America. Prior to joining TSMC in 1997 Rick was Vice President and General Manager of National Semiconductor’s Military and Aerospace Division. He joined National in 1979. Before that, Rick was an officer in the U.S. Army. He earned his Bachelor of Science degree from the United States Military Academy at West Point.

According to Rick attendance was up from last year which I certainly agree with. I counted 1008 seats in the main auditorium and estimate that 95% of them were taken. This does not include the partners manning the booths in the exhibition room next door.

Rick presented the TSMC vision and mentioned some interesting numbers:

*TSMC has more than 5,000 silicon validated IP available today, WOW! I have been through the TSMC silicon validation process many times and let me tell you it is rigorous to say the least.

*TSMC has invested $1.5B in design enablement thus far in 2012!

*TSMC in 1987 had one fab, a $20M CAPEX, 30 products and shipped 3,600 wafers

*TSMC in 2012 has 11 fabs, 5,498 different technologies, 12,569 products, $50B CAPEX, 615 customers, and a 15.3M wafer capacity!

Rick mentioned that his decision to join the semiconductor industry was based on the opportunity to change the world. I wish I could say the same. 30 years ago I was a starving college student and my decision was financial. I knew there was big money to be made in Silicon Valley and I wanted some. Looking back however we did change the world and there is still plenty of money to be made in doing so.

Next up was Dr. Mark Liu. Mark is TSMC’s Executive Vice President and Co-Chief Operating Officer. He joined TSMC in 1993 as an Engineering Manager. Prior to that Mark served in a number of technical capacities first with AT&T Bell Laboratories as a principal investigator in High Speed Electronics Research and later at Intel Corporation where he developed process technologies for Intel’s 32-bit microprocessors and flash memory products. Mark is a member of the Board of Directors of Silicon System Manufacturing Company in Singapore. He received Ph.D. degrees in electrical engineering and computer science from the University of California, Berkeley.

I met Mark when I toured Fab 12 in 2010, I blogged about it HERE. A memorable experience for sure. Mark ramped up TSMC’s first 200mm fab in 1993 and has been building fabs for TSMC ever since. Mark talked about “The Internet of Things” and what 2030 will look like. Mark also stated that:

*The TSMC 20nm design ecosystem (EDA and IP) are available today

*20nm is close to complete and will be in production next year

*TSMC will have three fabs for 20nm.

Next up was Dr. Cliff Hou, Cliff is vice president of R&D. Cliff’s door and mind is always open for new technology discussions and debates on the future of the semiconductor ecosystem. Cliff joined TSMC in 1997 and was appointed TSMC’s Vice President of Research and Development (R&D) in 2011. He was previously Senior Director of Design and Technology Platform where he established the company’s technology design kit and reference flow development organizations. He also led TSMC’s in-house IP development teams from 2008 to 2010. Cliff holds 20 U.S. patents and serves as a board member of Global Unichip Corp. He received his Ph.D. in electrical and computer engineering from Syracuse University.

Cliff added that:

*20nm engagements with partners and customers started much earlier

*TSMC overcame 20nm challenges through collaboration

*16nm FinFET will require even deeper collaboration

Cliff also mentioned that at 40nm partners and customers started design work when the PDK was release 0.5, at 28nm design work started at PDK 0.1, at 20nm design work started at PDK .05, and 16nm will start at PDK .01. The 20nm PDK 1.0 and 20nm foundation IP is silicon validated and available today with customer tape-outs expected in Q1 2013. 16nm PDK .1 will be available in Q1 2013 with the production version PDK 1.0 scheduled in Q4 2013.

The most interesting thing for me was the FinFET discussions and there were plenty of them which I will blog about separately. For those of you who don’t know about FinFETS start here with the FinFET Wiki. 2013 will be the year of the FinFET, absolutely!

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TSMC dilemma: Cadence, Mentor or Synopsys?

TSMC dilemma: Cadence, Mentor or Synopsys?
by Eric Esteve on 10-18-2012 at 4:49 am
Categories: Cadence, EDA, Foundries, Siemens EDA, Synopsys, TSMC

Looking at the Press Release (PR) flow, it was interesting to see how TSMC has solved a communication dilemma. At first, let’s precise that #1 Silicon foundry has to work with each of the big three EDA companies. As a foundry, you don’t want to lose any customer, and then you support every major design flow. Choosing another strategy would be stupid.

The first PR came on October 12, about Chip on Wafer on Substrate tape out, here is an extract: “TSMC today announced that it has taped out the foundry segment’s first CoWoS™ (Chip on Wafer on Substrate) test vehicle using JEDEC Solid State Technology Association’s Wide I/O mobile DRAM interface… A key to this success is TSMC’s close relationship with its ecosystem partners to provide the right features and speed time-to-market. Partners include: Wide I/O DRAM from SK Hynix; Wide I/O mobile DRAM IP from Cadence Design Systems; and EDA tools from Cadence and Mentor Graphics.”

As you can see, both design tools from Cadence and Mentor are mentioned, and Cadence can be honored: the test vehicle is based on Wide I/O mobile DRAM IP from the company. We will have a look at Wide I/O more in depth soon in this blog.

Cadence and Mentor? Look like one is missing!

Then, today, the industry was awarded that Synopsys has “received TSMC’s 2012 Interface IP Partner of the Year Award for the third consecutive year. Synopsys was selected based on customer feedback, TSMC-9000 compliance, technical support excellence and number of customer tape-outs. Synopsys’ DesignWare Interface IP portfolio includes widely used protocols such as USB, PCI Express, DDR, MIPI, HDMI and SATA that are offered in a broad range of processes from 180 nanometer (nm) to 28nm.”

If you want to know more about the Interface IP market, weighting over $300 million in 2011, you should take a look at this post

The PR about the Chip on Wafer on Substrate (CoWoS) from TSMC shows that Cadence invests to develop the memory controller technology of the near future, to be used for 3D-IC on mobile applications. I suggest you to read this excellent article from Paul McLelan, so you will understand how work CoWoS from a Silicon technology standpoint.

I will rather focus on the Wide I/O Memory Controller. Here is the description of the key features, as described by Cadence:
Key Features

  • Supports Wide I/O DRAM memories compliant with JESD229
  • Supports typical 512-bit data interface from SoC to DRAM (4 x 128 bit channels) over TSV at 200MHz offering more than 100Gbit/sec of peak DRAM bandwidth
  • Independent controllers for each channel allow optimization of traffic and power on a per-channel basis
  • Supports 3D-IC chip stacking using direct chip-to-chip contact
  • Supports 2.5D chip stacking using silicon interposer to connect SoC to DRAM
  • Priority and quality-of-service (QoS) features
  • Flexible paging policy including autoprecharge-per-command
  • Two-stage reordering queue to optimize bandwidth and latency
  • Coherent bufferable write completion
  • Power-down and self-refresh
  • Advanced low-power module can reduce standby power by 10x
  • Supports single- and multi-port host busses (up to 32 busses with a mix of bus types)
  • Priority-per-command (AXI4 QoS)
  • BIST algorithm in hardware enables high-speed memory testing and has specific tests for Wide I/O devices

It’s amazing! During the last ten years, we have seen a massive move from parallel to serial interface, think about PCI moving to PCI Express, PATA being completely replaced by SATA in storage application in less than 5 years, and the list is long. With the Wide I/O concept, we can see that a massively (512-bit) parallel interface, running at 200 MHz (to be compared with LPDDR3 at 800 MHz DDR), can offer both a better bandwidth up to 17 GB/s, and a better power per transfer performance than LPDDRn solution.

Anything magic here? The higher performance in term of bandwidth can be easily explained: adding enough 64-bit wide busses will allow passing LPDDR3 performance. But the reason why the power per transfer is better is more subtle: because it’s a 3D technology, the connection between the SoC and the DRAM will be made in the 3[SUP]rd[/SUP] (vertical) dimension, as shown in the picture from Qualcomm : thus, the connection length will be shorter than any connection made on a board. Moreover, the capacitance (due to the bumping or bonding material and to the track on the PCB) will be minimized with 3D connection. Then the power per bit transferred at a certain frequency. I did not checked how this was computed, but I am not shocked by this result…

So, Wide I/O memory controller looks like a superb new technology developed by Cadence, the mobile market is healthy enough (an understatement!) to decide to introduce the technology, but, as mentioned by Qualcomm on the above picture “Qualcomm want this but also competitive pricing”…

Eric Esteve from IPNEST

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Soft IP Quality Standards

Soft IP Quality Standards
by Paul McLellan on 10-09-2012 at 1:08 pm
Categories: EDA, Foundries, TSMC

As SoC design has transformed from being about writing RTL and more towards IP assembly, the issue of IP quality has become increasingly important. In 2011 TSMC and Atrenta launched the soft IP qualification program. Since then, 13 partners have joined the program.

IP quality is multi-faceted but at the most basic level, an IP block needs to do two things: it needs to meet its specification (for example, adhering to the protocol standard for a network interface) and it needs to be easy to implement into the design. Ideally, the IP itself does not need to be changed at all, this would be an indication of lack of IP quality and immediately increases the verification cost.

October 16th is the TSMC Open Innovation Platform Ecosystem Forum at the San Jose convention center. Anuj Kumar of Atrenta will discuss the TSMC IP Kit, which is a joint development between TSMC and Atrenta using the SpyGlass platform for IP handoff analysis and validation. The presentation will be at 11am. In particular he will discuss the new version of the IP Kit, TSMC IP Kit 2.0, currently under joint development between Atrenta and TSMC. This version of the kit adds physical analysis of the IP (such as routing congestion) as well as advanced formal metrics the explore the ease of verification of the IP.

Anuj will review the tests that are part of the Kit, show example quality metrics and DataSheet reports, and discuss the kind of design issues that have been uncovered and fixed as a result of the program. He will present the timeline for implementation of IP Kit 2.0 and the results of the testing of IP Kit V2.0 with IP partners.

Information about the TSMC OIP Ecosystem Forum is here. Information about IP Kit is here. As well as Anuj presenting, Atrenta will also be exhibiting at booth #405.