Mentor at TSMC Technology Symposium

Mentor at TSMC Technology Symposium
by glforte on 03-29-2013 at 11:41 am

TSMC will host their annual technology symposium at several locations in the U.S. on April 9th in San Jose, April 16th in Austin, and April 23rd in Boston. TSMC will discuss the market outlook, design enablement, and technology for high-speed computing, mobile communications, connectivity and storage, CIS, embedded flash, power ICs, and MEMS.

Mentor Graphics will host a booth at the conference where you can learn more about Mentor’s reference flows, and tools for IC physical design, verification, DFM, silicon testing and yield improvement. Experts will be available to discuss special topics such as advanced fill requirements, double patterning, design for reliability, cell-aware testing and IJTAG.

To learn more and register,click here.


TSMC on Collaboration: JIT Ecosystem Development

TSMC on Collaboration: JIT Ecosystem Development
by Paul McLellan on 03-27-2013 at 2:02 pm

Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry’s Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be designed with the EDA tools already out there. Yes, new factors like signal integrity would grow in importance but this happened over several process generations and so was incremental. Basically, designers would wait for the first release of the Spice decks and the DRC rule decks and then get going.

This doesn’t work any more. Since then each process generation has a major discontinuity:

  • 45nm: power must be addressed
  • 28nm: high-K metal gate
  • 20nm: double patterning
  • 16nm: FinFET
  • 10nm: multiple patterning and spacer

These discontinuities mean that foundries such as TSMC have to work closely with EDA suppliers such as Synopsys to ensure that the tools are ready when the process is ready. Otherwise they face the problem of building a $5B fab and not having any designs ready to run in it for a year. For example, without double patterning aware place & route, and layout editors, DRCs etc it is not possible to do a 20nm design.

This is happening in an environment where the number of tapeouts is not increasing, and is probably declining. But the number of wafers needed in production is increasing exponentially. This makes it critically important to hit the volume and yield-learning ramps for a new process. Wafers that are not manufactured don’t really come back, the end-user will have purchased another product. TSMC is increasing its capacity at a 31% CAGR. That’s a lot of wafer starts. Better make sure there are really wafers to start.

Another factor that has been growing in importance is the increasing use of IP in SoC designs. This means that not only do EDA tools need to be ready to go when the process is ready, but IP needs to be ready too. It is hard to do an SoC design without DDRx, PCIe, USB and so on.


So TSMC needs to have 3 parallel collaboration tracks:

  • working with EDA suppliers to ensure that the gotcha new features such as double patterning or FinFETs in the new process have full support in the tools
  • working with IP suppliers to ensure that IP is ready in a timely manner. It may not be possible to have all IP available when the process is ready, for both technical (IP suppliers need the tools and the process to be reasonably stable to get work done) and economic (there is a lot of IP and it can’t all be created in parallel
  • working with lead design groups to ensure that the process matches their needs, that they have the PDKs and design kits they require and so on

The goal is to have everything come together so that when the process is ready and the fab is ready to ramp to volume, that the designs are there. In turn that requires IP and tools to be there to get the designs done.


The next process, 16nm, is a FinFET process so the new challenges largely are around the transistors (the metal fabric is basically unchanged from 20nm). Although FinFETs are wonderful from some points of view (low leakage, high current, lower voltage) they have some disadvantages too (higher parasitic capacitance, higher parasitic resistance due to the MEOL local interconnect, quantized device widths). The biggest challenge has probably been RC extraction accuracy, although that seems to be as good with FinFET as at 28nm now.

The goal for future processes is:

  • around 2X increase in gate-density per node. With no EUV at 10nm this will get challenging
  • 15% speedup with 25% power reduction per node. This should be easier than the area reduction
  • And although Cliff didn’t mention it, another major challenge is to keep the cost per wafer in line so that the 2X increase in gate-density also shows up as a cost reduction

So collaboration within the TSMC Open Innovation Platform (OIP) is the only way to address these types of challenge and get everyone to the finish line at the same time.

And with that, Cliff Hou went to get on a plane back to Taiwan having only flown in yesterday!


Unlocking the Full Potential of Soft IP

Unlocking the Full Potential of Soft IP
by Daniel Payne on 03-22-2013 at 11:32 am

EDA vendors, IP suppliers and Foundries provide an eco-system for SoC designers to use in getting their new electronic products to market quicker and at a lower cost. An example of this eco-system are three companies (TSMC, Atrenta, Sonics) that teamed up to produce a webinar earlier in March called: Unlocking the Full Potential of Soft IP.


Continue reading “Unlocking the Full Potential of Soft IP”


Synopsys ♥ TSMC!

Synopsys ♥ TSMC!
by Daniel Nenni on 03-14-2013 at 8:00 am

Dr. Paul McLellan and I will be covering the Silicon Valley SNUG live again this year. Unfortunately we are only allowed to see the keynotes (same thing with CDNLive) but they look very good:

Keynote Address: Massive Innovation and Collaboration into the “GigaScale” Age!
Aart de Geus, Chairman and co-CEO, Synopsys, Inc.

The semiconductor industry is on the bridge to a new world of complexity empowered by smaller dimensions, new transistor types, enormous IP reuse, and a focus on the great potential of electronic systems. In other words, the GigaScale Age is upon us! In addition, our customers are facing uncertain markets where merely making a better version of their last product is not sufficient. To survive and thrive in new and unknown markets, designers and their ecosystem partners are accelerating both their innovation and their collaboration with key partners. They expect the same from their EDA, IP and services partners. In his presentation, Aart will give an overview of the enormous amount of recent innovation and collaboration happening at Synopsys as we enable “Moore’s Law plus, plus” for yet another decade!

Technology Keynote – “From Crystal Ball to Reality — The impact of Silicon IP on SoC Design”
Sir Hossein Yassaie, PhD, Chief Executive Officer, Imagination Technologies Group

SoCs have transformed the semiconductor and electronics industries, integrating staggering breadth of functionality and performance into highly cost-effective, low power but complex single-chip solution platforms. However, there has been another transformation: many of the major functional blocks on today’s SoCs are provided by Silicon IP providers rather than designed in-house. Hossein will review some of the important technological and market trends in key segments and discuss how the IP industry is helping to create the ability to translate vision into reality , and to constantly enhance it. He will touch on key functional blocks in modern SoCs explaining how the GPU is becoming the new driving force not only for modern applications but also for design methodologies and process technologies, and how heterogeneous processing is transforming the way SoCs handle key user applications such as UI’s, gaming, multimedia and more.

Technology Keynote – “Collaborate to Innovate – A Foundry’s Perspective on Ecosystem
Dr. Cliff Hou, Vice President, Research & Development, TSMC

Ecosystem refers to a symbiotic, co-dependent, co-evolutionary and multiplicative relationship among its constituents. The semiconductor industry represents one of the largest business ecosystems in the world where the collective diversity and creativity has fundamentally reshaped the human society. As process scaling continues toward the atomic level, challenges abound and stakes are never higher. In this talk, we will offer a foundry perspective of the semiconductor ecosystem and how, through close collaboration, we combine individual specialties and resources to innovate and move the industry forward. Specifically, we will discuss how the collaboration with EDA is becoming ever closer, earlier and wider to enable designs concurrently with process development, even especially at the advanced nodes.

SNUG Around the world:
[TABLE]
|-
| Silicon Valley
| March 25-27, 2013
|-
| Boston
| September 12, 2013
|-
| Austin
| September 18, 2013
|-
| Canada
| October 1, 2013
|-
| Germany
| May 14, 2013
|-
| United Kingdom
| May 16, 2013
|-
| France
| June 11, 2013
|-
| Israel
| June 18, 2013
|-
| India
| June 12-13, 2013
|-
| Japan
| July 12, 2013
|-
| China
| August 22, 2013
|-
| Taiwan
| August 20-21, 2013
|-
| Singapore
| August 16, 2013
|-

As I mentioned in my blog Synopsys ♥ FinFETs, Synopsys knows FinFETs so be sure to see the FinFET tracks. Paul and I also get to attend the press lunch and hopefully, like last year, an hour roundtable with Aart. It is a great experience to hang with semiconductor people wearing SemiWiki shirts and to get recognized and even photographed. My wife rolls her eyes when it happens and makes me take out the trash when I get home to keep me grounded. But seriously, we all appreciate your support and encouragement and it is a pleasure to collaborate with you.

Note: TSMC’s Dr. Cliff Hou gets a coveted keynote so clearly Synopsys loves TSMC! Cliff would be a great addition to the Synopsys board dontcha think? I will see what I can do…..

Since 1991, SNUG (the Synopsys Users Group) has represented a global design community focused on accelerating innovation. Today, as the electronics industry’s largest user conference, SNUG brings together nearly 9,000 Synopsys tool and technology users across North America, Europe, Asia and Japan. In addition to peer-reviewed technical papers and insightful keynotes from industry leaders, SNUG provides a unique opportunity to connect with Synopsys executives, Synopsys design ecosystem partners and members of your local design community. Join your fellow engineers at the SNUG in your region — you’ll leave with practical information you can use on your current projects and the inspiration to accelerate innovation.


Qualcomm and Intel Dynasty Scenario at 14nm

Qualcomm and Intel Dynasty Scenario at 14nm
by Ed McKernan on 03-08-2013 at 1:00 pm

At a different time, but certainly within the past 12 months, Paul Otellini was asked if Intel would be a Foundry for Qualcomm. His reply was that it did not leave a good taste in his mouth. Nevertheless it was not rejected and the door that remained open just a crack is likely to swing open for Qualcomm, the premier mobile silicon supplier in whom both Apple and Samsung are dependent, to win the Mobile Market. The hinge of fate rests in the hands of Andy Bryant, Chairman of Intel, who would need to EOL the Atom and the acquired Infineon baseband group to eliminate the competitive wall that would lead to not just a true Fab filling but would redraw the geopolitical map of the semiconductor industry. With Intel pouring another $13B of CapEx into its expanded 14nm footprint, there are only two possibilities that make sense: Qualcomm and Apple (the latter is now focused on TSMC). A marriage of Qualcomm baseband with Intel 14nm process technology could result in a scenario that would be a remake of Intel’s 1990s Pentium Dynasty.

The trend in the mobile industry for Samsung and Apple is to continue down the path of increased verticality. The Baseband Ecosystem maintains the high ground in tablets and smartphones and soon it will be a standard feature in x86 ultrabooks. Intel bought Infineon’s baseband group to complete the platform needed to compete in the broader mobile market. However, their efforts are still markedly behind that of Qualcomm and others. Bryant can continue the forced march with little to show or abandon the effort that blocks Qualcomm’s entry into the Fabs.

An article recently mentioned that Apple has hired a team of over 100 ex TI Engineers in Israel to create WiFi and Bluetooth solutions. The timeframe for these solutions is unknown but with $137B in the bank it is easy for Apple to acquire the talent that can create silicon solutions that end up replacing their current suppliers (i.e. Broadcom and Qualcomm). A net reduction of $20 of silicon in every iPhone, iPAD and perhaps Mac Airs could lead to saving the company up to $10B in the era of the Billion Unit+ mobile market that is arriving in the next couple of years. As they say a Billion here, a Billion there and pretty soon your talking real money.

The aggressiveness of Apple and Samsung in designing the key platform components while elbowing out other Fabless vendors at the Foundry has to be making Qualcomm nervous. The $25B+ in Qualcomm’s bank account leads all mobile players, except Apple. What if the cash is not enough of a cushion to prevent Apple or Samsung from hiring or buying the assets of Qualcomm’s competitors? If you think it unlikely, then one just has to review the staggering opportunity outlined above.

Under the Andy Bryant Regime, All product groups must now come clean on their true ROI of existing and new products. Atom processors fall way below the line of pulling their weight for a company that by next January will have spent $36B on Capex in the past three years. All of this to drive towards 22nm and 14nm dominance. In contrast to Atom, the Xeon and Ivy Bridge more than any other digital IC, except FPGAs, are delivering on a heavy positive cash flow. However, the dilemma in play is that mobile will be at least an order of magnitude larger than x86 powered PCs and the number of Fabs will matter in the end game.

The idea that a fast growing market could be on an accelerating path towards consolidation seems at odds with the concept that a rising tide lifts all boats. It took more than 50 years for the American auto industry to consolidate and yet the new mobile industry and the entire supply base may do so in less than 8 years from the time of the first iPhone introduction. It is in Apple and Samsung’s interest to accelerate the trend.

Juxtaposed to the Samsung and Apple vertical supply chain is the also heavily capitalized Fabs of Samsung, TSMC and Intel who race to be the ultimate winner at the leading edge, where all mobile silicon goes to maximize performance/watt while minimizing quiescent current. Intel’s leadership in the pre-mobile days was based on the x86 processor lock required for Windows and its process lead. The silicon supremacy shift away from processors and to the baseband and wireless infrastructure occurred faster than most imagined and the Intel acquisition of Infineon has proved to be too late in the game to help x86 Atoms make a dent in the market.

Now that the multi-billion unit, 4G enabled train has left the station, Intel has to catch up with its only true weapon and that is 14nm. Should Andy Bryant be able to sign a Foundry agreement with Qualcomm and redirect Intel’s massive design resources, there would be benefits in a number of areas for both companies. For Qualcomm, the ability to leverage Intel’s lower cost and much lower power 14nm would remove the competitive threats of Broadcom, nVidia, Mediatek and others. Samsung and Apple would have to think twice of continuing with their own internal wireless and baseband developments as Qualcomm moves into the mid range and low end markets at generous margins. The profit pool that would arise for Intel and Qualcomm would be staggering but it requires Intel give up its desire to own the chip inside the smartphone.

In return for enabling Qualcomm to clear the field, Intel would take a giant step towards rebalancing its Fabs relative to Samsung and TSMC in the mobile market. This move, with Qualcomm’s increased TAM exposure at the expense of its rivals, would be the equivalent of moving more than one Fab loading from TSMC over to Intel’s side of the ledger. For Intel the legacy x86 and Data Center business will still require some leading edge capacity, however a larger and larger percentage of processors will shift to a longer tail business model now that AMD competition has melted away. Intel will initiate other long tail fab deals, of which the 14nm Altera one is a perfect example.

The outcries from the former Otellini regime will be huge as the Atom and Infineon groups fight to remain relevant. The math is simple for Bryant. A $15 Atom processor at 5-10% or even 20% share in the smartphone market doesn’t come close to the revenue and margins that are available by opening up the Foundry to Qualcomm. Legacy Intel and Windows will remain together from tablets to PCs and servers as Win RT on ARM fades quickly into the sunset. By the end of 2013, I can envision a scenario where the partnership of Intel and Qualcomm is announced and the surprise to most is that they are no longer competitors at the platform level.

The tremors that will ripple through the semiconductor industry on an Intel – Qualcomm partnership will destabilize much of the mobile market and over time be seen as greater in magnitude than any other single event, including IBM’s selection of Intel’s 8088 for the original PC that sent Motorola packing. Qualcomm building products at Intel will lay low their wireless peers while Samsung and Apple take time to reconsider if their internal efforts are effectively moot. Intel’s ability to finally monetize its leading edge process will force Wall St. analysts to reconsider their valuation metrics. Beyond this though are additional second order derivatives acting as forcing functions. Will Apple consider a partnership at Intel so that they can develop the equivalent of a Snapdragon with their own ARM processor integrated with Qualcomm’s baseband?

For those of us who have watched the Semiconductor paint dry during the post Y2K decade, it is very interesting to consider what changes may occur as 14nm rolls out.

Full Disclosure: I am Long AAPL, QCOM, ALTR, INTC


TSMC ♥ Atrenta (Soft IP Webinar)

TSMC ♥ Atrenta (Soft IP Webinar)
by Daniel Nenni on 03-02-2013 at 4:00 pm

Back in 2011, TSMC announced it was extending its IP Alliance Program to include soft, or synthesizable IP. Around that time it was also announced that Atrenta’s SpyGlass platform would be used as the sole analysis tool to verify the completeness and quality of soft IP before being admitted to the program. Since then, the program has grown quite a bit. At present, I believe TSMC is closing in on 20 IP Partners that have qualified for inclusion in the program.

Why would TSMC want to focus on soft IP, and why the love affair with Atrenta? If you dig a little, it all makes sense. The third-party IP content in most chips today is 80 percent or more. The winner is no longer the company with the most novel circuit design, it’s the company who picks the best IP and successfully integrates it first. Because of the need for competitive differentiation, soft IP is becoming the preferred technology. You can tweak the content or function of soft IP; it’s a lot harder to do that with hard IP.

“Atrenta will be known for its relentless focus to deliver high quality, innovative products that help to enable design of the most advanced electronic products in the world. Our customers routinely benefit from improved quality, predictability and reduced cost. We maximize value for every customer, employee and shareholder.

So TSMC is on to something. Why not close the customer earlier in the design flow? If I have a choice of two foundry vendors, and one tells me about soft IP quality and one doesn’t, I know who I’m calling back. In sales terms, TSMC is expanding the reach of their “funnel”. So why is SpyGlass the only tool used at the top of that funnel? The aforementioned love affair between TSMC and Atrenta seems to be based on a one-stop shopping approach. TSMC’s quality check for its Soft IP Alliance looks at a lot – power, test, routing congestion, timing, potential synthesis issues and more. SpyGlass has been around a long time and covers all of those requirements. The other option is to work with multiple vendors to get the same coverage. It seems to me as long as SpyGlass is giving reliable answers, it will continue to be the sole tool at the gate to the Soft IP Alliance.

This doesn’t necessarily say Atrenta has a monopoly on the program. TSMC recently announced an endorsement of OaSys as another tool in the Soft IP program, see TSMC ♥ Oasys. I expect more such announcements. It’s a good idea for Soft IP suppliers to have multiple options to help achieve the quality and completeness TSMC is requiring.

If you want to learn more about what TSMC is up to with this program, I’m moderating a Webinar on March 5th that will cover all the details. See Unlocking the Full Potential of Soft IP (Webinar)for more information.

Agenda:

  • Moderator opening remarks – Daniel Nenni (SemiWiki)
  • The TSMC Soft IP Alliance Program – structure, goals and results – (Dan Kochpatcharin, TSMC)
  • Implementing the program with the Atrenta IP Kit – (Mike Gianfagna, Atrenta)
  • Practical results of program participation – (John Bainbridge, Sonics)
  • Questions from the audience (10 min)

Anyone who is contemplating the use of soft IP for their next SoC project should attend this webinar, absolutely!


TSMC (Lincoln) vs Samsung (Clinton) vs Intel (Washington)

TSMC (Lincoln) vs Samsung (Clinton) vs Intel (Washington)
by Daniel Nenni on 02-28-2013 at 9:00 am

Usually I sleep on long flights, if not, I watch movies and read. The Lincoln movie was playing on EVA Air this week which reminded me that Abraham Lincoln was one of the greatest U.S. Presidents. If I was asked to pick a U.S. President as a spokesperson for TSMC it would be Honest Abe Lincoln. Chairman Morris Chang said it best during his keynote, “We do not screw customers!” Samsung, on the other hand, chose Bill Clinton for their CES keynote which is also a good fit in my opinion (Clinton was impeached for lying and cheating but he is still a very popular President). For Intel I would choose George Washington, our founding father of microprocessors and GLOBALFOUNDRIES would be Barack Obama.

Associating with an American President is certainly good business since the U.S. market is the largest and Western culture is often emulated. Unfortunately honesty and decency is not always the top business priority in competitive markets so Abe Lincoln for a CES keynote would be a tough sell. Even with the incredible amount of intellectual property contained in semiconductors and consumer electronics, trust does not seem to be a prevailing factor.

Look at the Apple relationship with Foxconn. With horrible working conditions in their China factories that resulted in riots and suicides and many technology “leaks”, Apple still manufactures their all American iProducts at Foxconn. Look at Apple’s relationship with Samsung. With never ending legal actions Apple is still Samsung’s number one customer even though Samsung is Apple’s number one competitor. According to the press, Apple is moving away from Samsung but I’m not convinced it is a result of the quest for honesty and decency. From what I have learned Apple is using second source suppliers to negotiate better pricing from Samsung. The true test will be Apple’s 14nm SoC. Will Apple go back to Samsung or stay with TSMC? Apple will go back to Samsung, absolutely.

My experience at Avant! is another example. Even though the Avant! P&R tool was under indictment, customers still purchased the tool because it gave the best results making their semiconductor design faster, cheaper, more competitive. Profits over honesty and decency once again.

Sometimes our friends become our enemies, and sometimes our enemies become our friends

It is the classic tale of the scorpion and frog. A scorpion asks a frog to carry him across the water. The frog is afraid but the scorpion assures the frog that if he stings him it would be bad for both of them. The frog agrees and starts carrying the scorpion across the water but the scorpion stings the frog anyway because it is his nature. Profits are the nature of business so don’t be to surprised if you get stung by one of your friends.

Even with my bias against Samsung, my wife has informed me that we will be buying a new Samsung washer and dryer this year. She saw them at CES, they are clearly the smartest and best value, so honesty, decency, and my personal bias will not be a factor in the purchase decision. Unless of course I want to do the mountain of laundry my kids and I generate every week and I certainly do not. Laundry over ethics for sure.


TSMC ♥ Cadence

TSMC ♥ Cadence
by Daniel Nenni on 02-19-2013 at 11:00 am

In a shocking move TSMC now favors Cadence over Synopsys! Okay, not so shocking, especially after the Synopsys acquisitions of Magma, Ciranova, SpringSoft, and the resulting product consolidations. Not shocking to me at all since my day job is Strategic Foundry Relationships for emerging EDA, IP, and fabless companies.

Rick Cassidy, President of TSMC North America, keynoted the Cadence 2013 sales kick-off and had some very flattering things to say about Cadence. The most notable thing, for me anyway, is that TSMC will use more Cadence tools internally. Who cares? TSMC’s top customers care since EDA tools are an important form of communication, especially on the emerging process nodes. Even more important now since the days of multi-vendor reference flows may be a thing of the past.

Two big data points:

[LIST=1]

  • SpringSoft Laker Layout will be replaced with Cadence Virtuoso!
  • HSPICE will be replaced by Cadence Spectre and BDA AFS!

    According to my friends at SpringSoft, the Laker layout tool had a 70% market share in Taiwan including the foundries. Circuit design was still done with Cadence Virtuoso so the link between the two tools is critical. From what I understand, Synopsys will integrate the Laker layout tool intoCustom Designer so the interface between Laker and Virtuoso is in question. Why would Cadence or Synopsys want to spend precious resources supporting that interface? This should bring the Virtuoso market share number up a few points. The other winner in this product transition is Tanner EDA who now owns the affordable layout tool market segment.

    HSPICE has been the gold simulation standard ever since I can remember. I met the Meta Software guys in 1984 when I worked for Data General. We supplied them a machine to get HSPICE ported over for a common customer. A $1M computer was delivered to their garage for the port and the paperwork was signed on their kitchen table. Avant! acquired Meta, Synopsys acquired Avant!, and the HSPICE dynasty continues to this day.

    Magma FineSim was the biggest challenge to HSPICE and one of the reasons Synopsys paid a premium for Magma (my opinion). There were literally thousands of FineSim licenses doing the heavy simulation lifting while HSPICE was used for sign-off. The FineSim customer list included top semiconductor companies, top IP companies, and foundries alike. After the Magma acquisition, quite a few FineSim customers turned to Berkeley Design Automation in order to get the speed of FineSim and maintain two SPICE vendors. SPICE models bridge the information gap between semiconductor design and manufacturing so customers want to know what a foundry uses internally making this is a VERY big opportunity for BDA.

    Before you get too excited about the TSMC ♥ Cadence thing take a look at who is keynoting CDNLive next month: Young Sohn, President & Chief Strategy Officer, Samsung Electronics. Even more interesting, Cadence recently announced the election of Young K. Sohn, president and chief strategy officer of Samsung Electronics to its board of directors. Given that Samsung is TSMC’s biggest threat to their foundry dynasty I find this all intriguing. Certainly better than the reality TV shows that my daughters make me watch!


  • Using Soft IP and Not Getting Burned

    Using Soft IP and Not Getting Burned
    by Daniel Payne on 02-07-2013 at 10:11 am

    The most exciting EDA + Semi IP company that I ever worked at was Silicon Compilers in the 1980’s because it allowed you to start with a concept then implement to physical layout using a library of parameterized IP, the big problem was verifying that all of the IP combinations were in fact correct. Speed forward to today and our industry still faces the same dilemas, how do you assemble a new SoC designed with hard and soft IP, and know that it will be functionally and physically correct?

    They say that it takes a village to raise a child, so then in our SoC world it takes collaboration between Foundry, IP providers and EDA vendors to raise a product. One such collaboration is between:

    These three companies are hosting a webinar on Tuesday, March 5, 2013 at 9AM, Pacific time to openly discuss how they work together to ensure that you can design SoCs with Soft IP and not get burned.

    Agenda

    • Moderator opening remarks
      Daniel Nenni (SemiWiki) (5 min)

    • The TSMC Soft IP Alliance Program – structure, goals and results
      (Dan Kochpatcharin, TSMC) (10 min)

    • Implementing the program with the Atrenta IP Kit
      (Mike Gianfagna, Atrenta) (10 min)

    • Practical results of program participation
      (John Bainbridge, Sonics) (10 min)

    • Questions from the audience (10 min)

    Speakers

    Daniel Nenni
    Founder, SemiWiki
    Daniel has worked in Silicon Valley for the past 28 years with computer manufacturers, electronic design automation software, and semiconductor intellectual property companies. Currently Daniel is a Strategic Foundry Relationship Expert for companies wishing to partner with TSMC, UMC, SMIC, Global Foundries, and their top customers. Daniel’s latest passion is the Semiconductor Wiki Project (www.SemiWiki.com).


    John Bainbridge
    Staff Technologist, CTO office, Sonics, Inc.
    John joined Sonics in 2010, working on System IP, leveraging his expertise in the efficient implementation of system architecture. Prior to that John spent 7 years as a founder and the Chief Technology Officer at Silistix commercializing NoC architectures based upon a breakthrough synthesis technology that generated self-timed on-chip interconnect networks. Prior to founding Silistix, John was a research fellow in the Department of Computer Science at the University of Manchester, UK where he received his PhD in 2000 for work on Asynchronous System-on-Chip Interconnect.


    Mike Gianfagna
    Vice President, Corporate Marketing, Atrenta
    Mike Gianfagna’s career spans 3 decades in semiconductor and EDA. Most recently, Mike was vice president of Design Business at Brion Technologies, an ASML company. Prior to that, he was president and CEO for Aprio Technologies, a venture funded design for manufacturability company. Prior to Aprio, Mike was vice president of marketing for eSilicon Corporation, a leading custom chip provider. Mike has also held senior executive positions at Cadence Design Systems and Zycad Corporation. His career began at RCA Solid State, where he was part of the team that launched the company’s ASIC business in the early 1980’s. He has also held senior management positions at General Electric and Harris Semiconductor (now Intersil). Mike holds a BS/EE from New York University and an MS/EE from Rutgers University.


    Dan Kochpatcharin
    Deputy Director IP Portfolio Marketing, TSMC
    Dan is responsible for overall IP marketing as well as managing the company IP Alliance partner program.
    Prior to joining TSMC, Dan spent more than 10 years at Chartered Semiconductor where he held a number of management positions including Director of Platform Alliance, Director of eBusiness, Director of Design Services, and Director of Americas Marketing. He has also worked at Aspec Technology and LSI Logic, where he managed various engineering functions.

    Dan holds a Bachelor of Science degree in electrical engineering from UC Santa Barbara, a Master of Science in computer engineering, and an MBA from Santa Clara University.

    Registration
    Sign up here.


    Wall Street Does NOT Know Semiconductors!

    Wall Street Does NOT Know Semiconductors!
    by Daniel Nenni on 01-20-2013 at 6:00 pm

    In my never ending quest to promote the fabless semiconductor ecosystem I cannot pass up a discouraging word about one of the oldest financial services companies. You can consult with me for $300 per hour to answer your questions about the semiconductor industry on the phone or you can buy me lunch and get it in person (lunch will probably cost you more). The people who hire me are usually financial types (hedge fund managers etc…) but I also get called by semiconductor companies for market strategies and such. SoCs are a popular topic now and things get busy when quarterly results come in for TSMC, Intel, and the fabless guys in the mobile market segment. The fun part is taking apart analyst reports like the recent one from Morgan Stanley about TSMC.

    Since its founding in 1935, Morgan Stanley and its people have helped redefine the meaning of financial services. The firm has continually broken new ground in advising our clients on strategic transactions, in pioneering the global expansion of finance and capital markets, and in providing new opportunities for individual and institutional investors. Click below to see a timeline of Morgan Stanley’s growth, which parallels the history of modern finance.

    To start, look at the Morgan Stanley Wikipedia page which lists controversies and lawsuits with fines in the hundreds of millions of dollars.

    TSMC released Q4 2012 numbers during last week’s conference call. You can read the Seeking Alpha transcript HERE. I’m a big fan of the Seeking Alpha transcripts, reading is much better than listening, unfortunately the Seeking Alpha analysts don’t know semiconductor either but more on that later.

    Per Morgan Stanley:

    [LIST=1]

  • 28nm is surprising on the upside (DUH)
  • 28nm Margins above expectations (DUH)
  • 20nm node to be bigger than 28nm (WRONG)
  • TSMC 6.5% Q1 revenue drop (WRONG)

    Disclaimer: This information came from a phone call so it may not be 100% accurate but it has been repeated by other analysts so they are valid discussion points.

    Morgan Stanley and others were surprised at the TSMC Q4 financial numbers which they should not have been. As I blogged before, 28nm will be the most successful node we have seen in a long time (in all regards) and TSMC owns it, thus the high margins. To be fair, TSMC warned that Q4 could be soft but I blogged otherwise. TSMC is a conservative company and can certainly play the Wall Street game. On the other hand, I would rather see ACCURATE forecasts from analysts so we can do business without shortages, layoffs, and the other things that go along with bad business decisions.

    In what way will 20nm be bigger than 28nm? Compare the value proposition of 28nm and 40nm versus 20nm and 28nm in regards to price, performance, and power consumption. The value proposition of 20nm is less than half of 28nm meaning some companies will do limited tape-outs at 20nm, some are even skipping 20nm completely in favor of 14nm FinFETs which should ramp shortly after 20nm. Samsung, GLOBALFOUNDRIES, and TSMC will all use Gate-Last HKMG and have 20nm production simultaneously so heated competition will be a factor. TSMC has the advantage of being on their second generation of the Gate-Last HKMG experience since Samsung and GLOBALFOUNDRIES used Gate-First at 28nm which did not yield as well. Samsung has the “Brute Force” 20nm advantage with what seems like unlimited resources and fab capacity. Samsung is also an IDM with internal SoC/VLSI design experience. GLOBALFOUNDRIES has the advantage of being the designated second source foundry by companies like Qualcomm and other big fabless companies that see Samsung as a ruthless competitor. The GLOBAFOUNDRIES New York fab is 20nm so customers can keep their IP protected under American law.

    Bottom line: 20nm is a completely different game than 28nm so any comparison will be much more complicated, be very careful who you listen to, my opinion.

    Q1 will be like Q4, underestimated, but that is all part of the Wall Street game. There is no stopping the mobile market, 28nm owns mobile, TSMC owns 28nm, simple as that. Seeking Alpha is still perpetuating the Apple at TSMC 28nm misinformation and, in general, I’m not impressed at all with their semiconductor coverage. If you read them do a quick author look up on LinkedIn. If they don’t have a profile there is probably a good reason for it. If they do, look for at least some semiconductor experience before investing your hard earned money their way.

    Also read: TSMC Apple Rumors Debunked!