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TSMC OIP Ecosystem Forum 2012

TSMC OIP Ecosystem Forum 2012
by Daniel Nenni on 10-07-2012 at 7:11 pm

The TSMC Open Innovation Platform® (OIP) Ecosystem Forum brings TSMC’s design ecosystem member companies together to share with our customers real-case solutions for customers’ design challenges and success stories of best practice in TSMC’s design ecosystem.


More than 90% of the attendees last year said “this forum helped them better understand the components of TSMC’s Open Innovation Platform” and “they found it effective to hear directly from TSMC OIP member companies.”

Please introduce yourself if you see me. It would be a pleasure to meet you!

REGISTRATION

This year, the forum will feature a day-long conference starting with executive keynotes from TSMC and ARMin the morning plenary session to outline future design challenges and roadmaps, as well as discuss a recent collaboration announcement, 30 selected technical papersfrom TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies, and an Ecosystem Pavilion featuring up to 80 member companies showcasing their products and services.

Agenda

San Jose Convention Center,
Tuesday , October 16th, 2012

[TABLE] cellpadding=”4″ style=”width: 97%”
|-
| colspan=”4″ align=”center” | Plenary Session
|-
| style=”width: 15%” | 08:00
| colspan=”3″ | Registration Opens
|-
| 09:00 – 09:10
| colspan=”2″ | Welcome Remarks
| style=”width: 29%” | TSMC NA Executive
|-
| 09:10 – 09:40
| colspan=”2″ | An Ecosystem for Innovation
| TSMC Executive
|-
| 09:40 – 10:10
| colspan=”2″ | TSMC Design Technology Update
| TSMC Executive
|-
| 10:10 – 10:40
| colspan=”2″ | ARM Feature Talk
| Inviting Executive Level Speaker
|-
| 10:40 – 11:00
| colspan=”3″ align=”center” | Coffee Break
|-

[TABLE] cellpadding=”4″ style=”width: 97%”
|-
| align=”center” style=”width: 15%” | [TABLE] cellpadding=”10″ style=”width: 100%”
|-
| align=”center” |
|-

| align=”center” width=”27%” | EDA Track
| align=”center” width=”29%” | IP Track
| align=”center” width=”29%” | EDA/IP/Services Track
|-
| 11:00 – 11:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | A Platform for the CoWoS Reference Flow
|-
| align=”center” valign=”top” | Mentor Graphics
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | TSMC IP Kit V2.0 – Enhancing Soft IP Quality Standards
|-
| align=”center” valign=”top” | Atrenta
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | SiP, 3D-IC & IPD Complement Flexible ASICs
|-
| align=”center” valign=”top” | GUC
|-

|-
| 11:30 – 12:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | How to Manage Variability and Double
Patterning at 20nm
|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | 1T-OTP – Non-Volatile Memory for
Mobile and Other Low-Power Applications
|-
| align=”center” valign=”top” | Sidense
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Timing Sign-off and Technology Migration Using Functionalized Timing Reports
|-
| align=”center” valign=”top” | IMEC
|-

|-
| 12:00 – 12:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Finding and Fixing Double Patterning Errors in 20nm Design
|-
| align=”center” valign=”top” | Mentor Graphics &
TSMC

|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Implementing and Optimising Graphics IP in SoCs
|-
| align=”center” valign=”top” | Imagination Technologies
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Truly Differentiated Memory Subsystems on TSMC’s Advanced Technology Nodes
|-
| align=”center” valign=”top” | eSilicon
|-

|-
| 12:30 – 13:30
| colspan=”3″ align=”center” valign=”top” | Lunch
|-
| 13:30 – 14:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Enabling 20nm Custom Design in Laker
|-
| align=”center” valign=”top” | Springsoft
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Advanced Silicon Design Methodology For Achieving 20nm Ready, Physical IP
|-
| align=”center” valign=”top” | Synopsys
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Publishing Innovation through IP Targeting TSMC Technology
|-
| align=”center” valign=”top” | Design & Reuse
|-

|-
| 14:00 – 14:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | 3D-IC Silicon Interposer IC Design Flow Using Cadence Encounter Digital Implementation (EDI) System
|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Comprehensive Embedded NVM Solution in Trusted Technology and Capacity Platform
|-
| align=”center” valign=”top” | eMemory
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | TMI: A Unified Compact Model Development Platform for 28nm & Beyond
|-
| align=”center” valign=”top” | Synopsys &
TSMC

|-

|-
| 14:30 – 15:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Verification of Power, Signal, and Reliability Integrity for 3D-IC/Silicon Interposer Designs
|-
| align=”center” valign=”top” | ANSYS / Apache
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Novel Low-Power Audio CODEC from 180nm to 28nm with Moore and More!
|-
| align=”center” valign=”top” | Dolphin Integration
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Design Methodology for Silicon-Accurate Jitter Analysis for 28nm Interface IP for 100GB Applications
|-
| align=”center” valign=”top” | Berkeley Design Automation &
Analog Bits

|-

|-
| 15:00 – 15:30
| colspan=”3″ align=”center” | Coffee Break
|-
| 15:30 – 16:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | TSMC Certification for Cadence 20nm RTL-to-GDSII Flow
|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Solving ESD, EOS and Latch-Up Requirements
– For Analog Interfaces in Advanced CMOS
– For Automotive Applications in TSMC’s BCD Platforms
|-
| align=”center” valign=”top” | SOFICS
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Comprehensive Simulation and Modeling Solutions for TSMC’s RF Platforms
|-
| align=”center” valign=”top” | Agilent / EEsof
|-

|-
| 16:00 – 16:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Double-Patterning Technology and Impact on 20nm Designs
|-
| align=”center” valign=”top” | Synopsys
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Enabling Design with Advanced Node Design IP for TSMC
|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Silicon-Accurate Mixed-Signal Fractional-N PLL IP Design
|-
| align=”center” valign=”top” | Berkeley Design Automation &
Silicon Creations

|-

|-
| 16:30 – 17:00
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Improved Design for Reliability Using Calibre PERC
|-
| align=”center” valign=”top” | Mentor Graphics
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Kilopass Roadmap for Advanced TSMC Processes
|-
| align=”center” valign=”top” | Kilopass
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Chip-Partitioning Trends in Systems Using Ultra Deep-Submicron SoCs
|-
| align=”center” valign=”top” | Cosmic Circuits
|-

|-
| 17:00 – 17:30
| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Automated Approach for Waiving Physical Verification Errors at IP
|-
| align=”center” valign=”top” | Mentor Graphics &
LSI

|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | Using Latest-Generation DDR4, LPDDR3 and
Wide-IO DRAM Devices with Chips in TSMC’s
Advanced 28nm and 20nm Processes
|-
| align=”center” valign=”top” | Cadence
|-

| align=”center” valign=”top” | [TABLE] cellspacing=”3″ style=”width: 100%”
|-
| align=”center” valign=”top” | CMOS Silicon Millimeterwave Design Closure on
Integrated Fullwave Electromagtic Simulation and
Extraction Platform with a Real Silicon Design Case
|-
| align=”center” valign=”top” | Lorentz &
Stanford University

|-

|-
| 17:30 – 18:00
| colspan=”3″ align=”center” | Networking and Reception
|-

Legal Notice:TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC’s corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.

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