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Silicon Correlation, Not EDA Marketing Sparkles!

Silicon Correlation, Not EDA Marketing Sparkles!
by Daniel Nenni on 10-07-2012 at 9:00 pm

It’s all about the silicon. It’s all about silicon correlation. TSMC Open Integration Platform should be renamed TSMC Silicon Correlation Platform or TSMC SCP. One of the problems I have with EDA technical papers today is that they are not silicon based. Anybody can put up slides with marketing sparkles on them but if you want qualified people to attend your presentation SHOW US THE SILICON CORRELATION!

Looking at the TSMC OIP papers this year you will see a trend of silicon correlation. TheBDA paper with Analog Bits for example. No marketing sparkles here, this one is on production high speed 28nm silicon:

Design Methodology for SiliconAccurate Jitter Analysis
for 28nm Interface IP for 100GB Applications

The successful design of a SerDes for 100GB Ethernet applications requires providing accurate quadrature outputs from a highperformance PLL at very low dissipated power levels. This paper describes the design and verification methodology of a 14GHz SerDes PLL for 100GB applications fabricated in TSMC 28nm technology which produces quadrature outputs and a measured output clock jitter < 0.3ps rms in under 12mW of power. The circuit verification methodology used to complete the jitter analysis relies on Berkeley Design Automation Analog FastSPICE (AFS) Platform and includes analysis of all device noise contributions, sensitivity analysis, RC parasitics, PVT and mismatch variations. The AFS Platform is certified in TSMC SPICEQualification Program, and AFS device noise subflow validated in TSMC AMS Reference Flow 2.0.

In this paper, we first review the design requirements for a SerDes IP macro for 100GB Ethernet applications, the OIFCEI28G*specifications, and the corresponding requirements on the highperformance PLL to meet the stringent jitter specifications. We describe the key effects that must be captured in any analysis to provide an estimate of the phase noise and jitter expected in TSMC 28nm technology. These include the impact of device noise, the identification of the top noise contributors, the capture of all postlayout effects, comprehensive PVT, and mismatch analysis using the AFS Platform.

We compare the alternate methods available to analyze phase noise and jitter (both random and deterministic) and summarize the advantages and disadvantages of each method. We first begin by looking at a traditional blocklevel analysis approach, using postlayout analysis results for each of the key components and using a linear transfer function model to complete the analysis. We then look at a new fullloop simulation approach using transient noise analysis. By using a systematic approach using new characterization techniques availble in the AFS Platform, we are able to achieve a fast turnaroundtime to complete a comprehensive analysis.

We then present the results for phase noise and jitter analysis and illustrate the excellent results obtained via the new fullloop simulation approach using AFS Transient Noise analysis. We demonstrate phase noise results with excellent correlation to silicon measurements to within 3 dB in the frequency ranges of interest. The resulting methodology extending simulationtosilicon correlation is now a standard practice for the development of our 28nm and 20nm interface IPs.

The TSMC Open Innovation Platform® (OIP) Ecosystem Forum brings TSMC’s design ecosystem member companies together to share with our customers real-case solutions for customers’ design challenges and success stories of best practice in TSMC’s design ecosystem.

More than 90% of the attendees last year said “this forum helped them better understand the components of TSMC’s Open Innovation Platform” and “they found it effective to hear directly from TSMC OIP member companies.”

This year, the forum will feature a day-long conference starting with executive keynotes from TSMC and ARMin the morning plenary session to outline future design challenges and roadmaps, as well as discuss a recent collaboration announcement, 30 selected technical papers from TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies, and an Ecosystem Pavilion featuring up to 80 member companies showcasing their products and services.


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