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TSMC OIP presentations available!

TSMC OIP presentations available!
by Beth Martin on 01-27-2014 at 6:27 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

Are you a TSMC customer or partner? If so, you’ll want to take a look at these presentations from the 2013 TSMC Open Innovation Platform conference:

Through close cooperation between Mentor and Synopsys, Synopsys Laker users can check with Calibre “on the fly” during design to speed creation of design-rule correct layout, including electrically-aware voltage-dependent DRC checks.

  • Verify TSMC 20nm Reliability Using Calibre PERC(Mentor Graphics)
    Calibre PERC was used in close collaboration with TSMC IO/ESD team to develop an automatic verification kit to verify CDM ESD issues for the N20 node.

  • EDA-Based DFT for 3D-IC Applications (Mentor Graphics)
    Testing of TSMC’s 2.5D/3D ICs implies changes to traditional Built-In Self-Test (BIST) insertion flows provided by commercial EDA tools. Tessent tools provide a number of capabilities that address these requirements while reducing expensive design iterations or ECOs, which ultimately translates to a lower cost per device.

  • Advanced Chip Assembly & Design Closure Flow Using Olympus-SoC (Mentor Graphics & NVIDIA)
    Mentor and NVIDIA discuss the chip assembly and design closure solution for TSMC processes, including concurrent MCMM optimization, synchronous handling of replicated partitions, and layer promotion of critical nets for addressing variation in resistance across layers.

More articles by Beth Martin…

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TSMC projects $800 Million of 2.5/3D-IC Revenues for 2016

TSMC projects $800 Million of 2.5/3D-IC Revenues for 2016
by Herb Reiter on 01-27-2014 at 11:00 am
Categories: Foundries, TSMC

At TSMC’s latest earnings call held mid January 2014, an analyst asked TSMC for a revenue forecast for their emerging 2.5/3D product line. C.C. Wei, President and Co-CEO answered: “800 Million Dollars in 2016 ”. TSMC has demonstrated great vision many times before. For me, an enthusiastic supporter of this technology, this statement represents a big moral boost. I had the opportunity to drive Synopsys’ support for the early TSMC reference flows and saw how this strategic move has paid off very well, for the entire Fabless EcoSystem. In my humble opinion, 2.5 and 3D ICs will have a great impact on our industry such as the TSMC’s reference flows have.

TSMC’s prediction for 2.5/3D revenues confirms what I see and hear: Several large companies and an impressive number of smaller ones are starting or are already relying on 2.5/3D technology for their products that will become available sometime between 2014-16. Why rely on 2.5/3D technology? Because continued shrinking of feature sizes, including FinFETs, is no longer economical for many applications. Likewise, wire-bonded multi-die solutions or package-on-package can no longer meet performance- and power requirements.

How can busy engineering teams quickly evaluate and choose the best alternative between current and the new 2.5 or 3D-IC solutions?

Based on the fact that this technology shifts a major part of the value creation into the package – packaging is becoming more important and must be considered PRIOR to silicon development. This new book expresses much of the packaging expertise Professor Swaminathan has gained in the last 20 years while working at IBM and teaching / researching at GeorgiaTech. Together with Ki Jin Han, they address most of the topics system- and IC designers need to consider when utilizing 2.5 and 3D-ICs solutions. Professor Swaminathan is also accumulating hands-on 2.5 and 3D experiences as CTO of E-System Design, an EDA start-up in this field. Their 2.5/3D book is available at Amazon.com.

The book explains in Chapter 1 why interconnect delays and the related power dissipation are constraining designers and how Through-Silicon-Vias (TSVs) help to finally break down the dreaded “Memory Wall”. Either a 2.5D IC (die side-by-side on an interposer) OR a 3D IC (vertically stacked die) solution can better meet the performance, power, system cost, etc requirements. But before expensive implementation is started, the various options available in either need to be objectively evaluated. Both solutions increase bandwidth while lowering power dissipation, latency and package height. In addition, they simplify integration of heterogeneous functions in a package, for example combining a large amount of memory with a multi-core CPU or adding analog/RF circuits to a logic die.

Chapter 2’s primary target audience is modeling and design tools developers. It explains how to accurately simulate the impact of TSVs, solder balls and bonding wires on high-speed designs – information also useful for package and IC designers.

Chapter 3 dives into a lot of practical considerations for designing with the above mentioned IC building blocks.

Chapter 4 focuses on signal integrity challenges, coupling between TSV as well as power and ground plane requirements. Both silicon and glass interposers are covered.

Chapter 5 addresses power distribution and thermal management and Chapter 6 looks at future concepts currently in development for solving 2.5/3D-IC design challenges.

The many formulas and examples in this book make it a great reference for experienced IC and package designers.

Herb@eda2asic

lang: en_US

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Is Altera Leaving Intel for TSMC?

Is Altera Leaving Intel for TSMC?
by Daniel Nenni on 01-24-2014 at 9:00 am
Categories: Foundries, Intel Foundry, TSMC

There is a rumor making the rounds that Altera will leave Intel and return to TSMC. Rumors are just rumors but this one certainly has legs and I will tell you why and what I would have done if I were Altera CEO John Daane. Altera is a great company, one that I have enjoyed working with over the years, but I really think they made a serious mistake at 14nm, absolutely. Altera moving to Intel was not necessarily the mistake, in my opinion it is how they went about it.

The rumor started here:

“Altera’s recent move [contacting TSMC] is probably due to its worry of the recent Intel’s 14nm process delay causing delay in its new product will let Xilinx win”
ChinaEconomic Daily News 12/2/13

It became more real when Rick Whittington, Senior Vice President of Drexel Hamilton, released a downgrade on Intel stock (INTC) from buy to hold titled “A Business Model in Flux”. There are more than a dozen bullet points but this one hit home:

While Altera’s use of 14nm manufacturing late this year wasn’t to ramp until mid-late 2015, it has been a trophy win against other foundries

A trophy win indeed, the question is why did Altera allow itself to be an Intel trophy? After working with TSMC for 25 years and perfecting a design ecosystem and early access manufacturing partnership, it was like cutting off your legs before a marathon.

The EDA tools, IP, and methodology for FPGA design and manufacturing are not mainstream to say the least. It is a very unique application which requires a custom ecosystem and ecosystems are not built in a day or even a year. Ecosystems develop over years of experience and partnerships with vendors. FPGAs are also used by foundries to ramp new process nodes which is what TSMC has done with Altera for as long as I can remember. This early access not only gave Altera a head start on design, it also helped tune the TSMC manufacturing process for FPGAs. Will Intel allow this type of FPGA optimization partnership for their “Intel Inside” centric processes? That would be like a flea partnering with a dog, seriously.

What would I have done? Rather than be paraded around like a little girl in a beauty pageant, Altera should have been stealthy and designed to both Intel and TSMC for FinFETs. Seriously, what did Altera REALLY gain by all of the attention of moving to Intel? Remember, TSMC 16nm is in effect 20nm using FinFETs. How hard would it have been to move their 20nm product to TSMC 16nm while developing the required Intel design and IP ecosystem? Xilinx will tape out 16nm exactly one year after 20nm and exactly one year before Altera tapes out Intel 14nm. Remember, Altera gained market share when they beat Xilinx to 40nm by a year or so.

Correct me if I’m wrong here but this seems to be a major ego fail for Altera. And if the rumor is true, which I hope it is for the sake of Altera, how is Intel going to spin Altera going back to TSMC for a quick FinFET fix?

More Articles by Daniel Nenni…..

lang: en_US

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ESD at TSMC: IP Providers Will Need to Use Mentor to Check

ESD at TSMC: IP Providers Will Need to Use Mentor to Check
by Paul McLellan on 01-22-2014 at 1:24 pm
Categories: EDA, Foundries, TSMC

I met with Tom Quan of TSMC and Michael Beuler-Garcia of Mentor last week. Weirdly, Mentor’s newish buildings are the old Avant! buildings where I worked for a few weeks after selling Compass Design Automation to them. Odd sort of déja vu. Historically, TSMC has operated with EDA companies in a fairly structured way: TSMC decided what capabilities were needed for their next process node, specified them and then the EDA companies developed the technology. It wasn’t quite putting out an RFP, in general TSMC wasn’t paying for the development, the EDA companies would recover their costs and more from the mutual customers using the next node.

The problem with this approach is it doesn’t really allow for innovation the originates within the EDA companies. Mentor and TSMC have spend the last couple of years working very cooperatively on a flow for checking ESD (electro-static discharge), latchup and EOS (electrical overstress). All of these can permanently damage the chip. ESD can be a major problem during manufacture, manufacturing test, assembly and even in the field. EOS causes oxide breakdown (some one-time programmable memories use this deliberately to program the bit cells, but when it kills other kinds of transistors it is a big problem). Like most things, it is getting worse from node to node, especially 20nm and 16nm. The gate oxide is getting thinner and so it is simply easier to damage. FinFETs are even more fragile.


Historically TSMC has had layout design rules for these types of issues. But they required marker layers to be added to the cells to indicate which checks should be done in which areas. This causes two problems. Adding the marker layers is tedious and not really very productive work. But worse, if the marker layers are wrong then checks can be omitted and, often, without causing any DRC violations to give a hint that there is a problem. Another issue is that the design rules from 20nm on are sometimes voltage dependent, again a solution that was addressed historically with marker layers. Even then, not all rules could be checked. In fact, previously 35% of rules could not be checked and 65% required marker layers to check.

This is increasingly a problem. It is obviously not life-threatening if the application processor in your smartphone fails (although obviously more than annoying). But medical, automotive and aerospace have fast growing electronic content and they have much higher reliability requirements. If your ABS system or your heart pacemaker fails it is a lot more than annoying.

So Mentor and TSMC decided that they wanted a flow for checking that didn’t require marker layers and covered all the rules. It would obviously need to pull in not just layout data, but netlist and other electrical data (voltage dependent design rules obviously require knowing the voltages). The flow is intended for checking IP as part of the TSMC9000 IP quality program.

This is built on top of Mentor’s PERC (programmable electrical rule checker). They focused on 3 areas where these problems occur:

  • I/Os (ESD is mostly a problem in I/Os)
  • IP with multiple power domains
  • analog

Voltage dependent DRC checking is another area of cooperation. Many chips today have multiple voltages. In automotive and aerospace these may include high voltages and, as a general rule, widely separated voltages require widely separated layout on the chip to avoid problems. Again, the big gains in both efficiency and reliability come from avoiding marker layers.


The current status is that Calibre PERC is available for full-chip checking 28nm, 20nm with 16nm in development. As part of the IP 9000 program it is available for IP verification for 20SoC, 16FF and 28nm. Use of Calibre PERC will become a requirement (currently it is just a recommendation) in 20nm, 16nm and below.


More articles by Paul McLellan…

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TSMC Responds to Intel’s 14nm Density Claim!

TSMC Responds to Intel’s 14nm Density Claim!
by Daniel Nenni on 01-21-2014 at 9:30 pm
Categories: Foundries, Intel Foundry, TSMC

TSMC responded to Intel’s 14nm density advantage claim in the most recent conference call. It is something I have been following closely and have written about extensively both publicly and privately. Please remember that the fabless semiconductor ecosystem is all about crowd sourcing and it is very hard to fool a crowd of semiconductor professionals, absolutely. To see Intel’s infamous density presentation click HERE.


First let’s take a look at what TSMC had to say:

Morris Chang – Chairman:So I now would ask Mark Liu to speak to TSMC’s competitiveness versus Intel and Samsung:

Let me comment on Intel’s recent graph shown in their investor meetings, showing on the screen. I — we usually do not comment on other companies’ technology, but this — because this has been talking about TSMC technology and, as Chairman said, has been misleading, to me, it’s erroneous based on outdated data. So I’d like to make the following rebuttal:

On this new graph, the vertical axis is the chip area on a large scale. Basically, this is compared to chip area reduction. On the horizontal axis, it shows the 4 different technologies: 32, 28; 22, 20; 14, 16-FinFET; and 10-nanometer. 32 is Intel technology, and 28 is TSMC technology so is the following 3 nodes, the smaller number, 20, around — 14-FinFET is Intel, 16-FinFET is TSMC. On the view graph shown at Intel investor meeting, it is with the gray plot, showing here. The gray plot showed the 32- and the 20-nanometer TSMC is ahead of the area scaling and — but — however, with 16, the data — gray data shows a little bit uptick. And following the same slope, go down to the 10-nanometer, was the correct data we show on the red line. That’s our current TSMC data. The 16, we have in volume production on 20-nanometer. As C.C. just mentioned, this is the highest density technology in production today.

We take the approach of significantly using the FinFET transistor to improve the transistor performance on top of the similar back-end technology of our 20-nanometer. Therefore, we leverage the volume experience in the volume production this year to be able to immediately go down to the 16 volume production next year, within 1 year, and this transistor performance and innovative layout methodology can improve the chip size by about 15%. This is because the driving of the transistor is much stronger so that you don’t need such a big area to deliver the same driving circuitry.

And for the 10-nanometer, we haven’t announced it, but we did communicate with many of our customers that, that will be the aggressive scaling of technology we’re doing. And so in the summary, our 10 FinFET technology will be qualified by the end of 2015. 10 FinFET transistor will be our third-generation FinFET transistor. This technology will come with industry’s leading performance and density. So I want to leave this slot by 16-FinFET scaling is much better than Intel’s set but still a little bit behind. However, the real competition is between our customers’ product and Intel’s product or Samsung’s product.

Morris Chang – Chairman:Thank you, Mark. In summary, I want to say the following: First, in 2014, we expect double-digit revenue growth and we expect to maintain or slightly improve our structural profitability. As a result, we expect our profit growth to be close to our revenue growth. In 2014, the market segment that most strongly fuels our growth is the smartphone and tablet, mobile segment. The technologies that fuel our growth are the 20-SoC and the 28 high-K metal gate, in both of which we have strong market share. In 2015, our strong technology growth will be 16-FinFET. We believe our Grand Alliance will outcompete both Intel and Samsung, outcompete.

If there is anyone out there that doubts these numbers please post in the comment section or send me a private email. I will follow up with a rebuttal blog based on feedback next week.

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Intel is NOT Transparent Again!

Intel is NOT Transparent Again!
by Daniel Nenni on 01-19-2014 at 9:00 am
Categories: Foundries, Intel Foundry, TSMC

Recent headlines suggest that Intel was not transparent about some of the products they showed at the CES keynote. Intel confirmed on Friday that they used ARM-based chips for some of the products but would not say which ones. When your company’s tag line is “Intel Inside” and you hold up a product during your keynote wouldn’t one assume that Intel was actually inside?

Today saying someone is not transparent really means they are being deceptive and when that someone is the CEO of a publicly traded semiconductor company it is serious business, my opinion. Even more glaring is the Intel claim of a 35% density advantage over TSMC at 14nm. This was presented during the November 21[SUP]st[/SUP] 2013 Intel analyst meeting. There is a barely noticeable disclaimer in the bottom right corner that says:

Sources: TSMC keynote, ARM Tech Con 2012, Oct. 30, 2012. Intel data alignment based on internal assessment.

This goes to my argument that Intel is NOT serious about the foundry business. They used a trade show marketing presentation from 2012 for this technical analysis? Is that the best the mighty Intel can do for competitive information?

Based on a thorough investigation by myself and just about every other company in the fabless semiconductor ecosystem this claim has proven to be absolutely FALSE. I write this now so when silicon is out and scrutinized we can go back and see who was telling the truth. Spoiler alert: It is not Intel!

The other interesting Intel news is that their big 14nm fab in Arizona will not be in production anytime soon. The delay was called a “minor correction”. The real reason for the delay, in my opinion, is so that Intel can continue to claim 80% capacity utilization so Wall Street does not downgrade INTC stock. If Intel counted idle fabs, their capacity numbers would be closer to 50% than 80%.

The other big news is that TSMC 20nm is in full production. We already knew this but it is nice to see TSMC talking about it:

“We have two fabs, fab 12 and fab 14 that complete the core of the 20nm-SoC. As a matter of fact, we have started production. We are in the [high]-volume [20nm] production as we speak right now,” said C. C. Wei, co-chief executive officer and co-president of TSMC, during a conference call with investors and financial analysts.

Do you remember last year TSMC said on a conference call that 20nm would be in volume production Q2 2014? And I said they were being cautious, that it would happen in Q1 2014? I know things, believe it. TSMC also said 20nm will account for 10% of wafer revenues in 2014 which would be more than $2B worth of 20nm wafers.

TSMC also did a FinFET update:

Talking at the company’s latest financial meeting, Mark Liu, TSMC co CEO, claimed its 16nm FinFET process is now ready for tape out and could be in volume production this year. “Our 16FinFET yield improvement has been ahead of our plan. This is because we have been leveraging the yield, learning from 20SoC. Currently, the 16FinFET SRAM yield is already close to that of the 20SoC process.”

Let’s not forget what Mark Bohr of Intel said about TSMC last year:

“Bohr claims in TSMC’s recent announcement it will serve just one flavor of 20nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed to mitigate leakage current, Bohr said.”

TSMC 16nm is a FinFET version of 20nm, right? Maybe Mark saw that in a marketing presentation years ago? Intel, you really are better than this. If you don’t have something transparent to say maybe you should say nothing at all.

More Articles by Daniel Nenni…..

lang: en_US

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Intel Wafer Pricing Exposed!

Intel Wafer Pricing Exposed!
by Daniel Nenni on 12-28-2013 at 12:00 pm
Categories: Foundries, Intel Foundry, TSMC

One of the big questions on Intel’s foundry strategy is: Can they compete on wafer pricing? Fortunately there are now detailed reports that support what most of us fabless folks already know. The simple answer is no, Intel cannot compete with TSMC or Samsung on wafer pricing at 28nm, 20nm, and 14nm.

In fact, recent reports have shown that Intel 32nm versus TSMC 28nm gives TSMC a 30%+ wafer cost advantage. At Intel 22nm versus TSMC 20nm the cost advantage is 35%+. This is an apple to apple comparison with Atom SoC versus ARM SoC silicon. Another key metric is capacity. During the recent investor meeting Intel CFO Stacy Smith claimed Intel was at 80% capacity so that is the number that was used in the wafer cost calculations for both Intel and TSMC. I question this number since Intel has three idle fabs (OR, AZ, Ireland) and TSMC 28nm was at 100% capacity up until recently but I digress…..

On the technical side we now know that, even with Intel’s superior process claims, TSMC 28nm SoCs easily beat Intel at 32nm in both power and performance. TSMC 20nm SoCs will again beat Intel 22nm. 14nm SoCs have yet to launch but one thing I can tell you is that Intel will NOT win business from TSMC’s top customers which will make up more than 50% of fabless revenues:

[LIST=1]

  • Qualcomm: TSMC and Samsung
  • Apple: TSMC and Samsung
  • NVIDIA: TSMC and Samsung
  • AMD: TSMC and GlobalFoundries
  • MediaTek: TSMC
  • Marvell: TSMC and Samsung
  • Broadcom: TSMC and Samsung
  • TI: TSMC
  • Spreadtrum: TSMC and Samsung
  • Xilinx: TSMC

    As you can see most of these customers will straddle TSMC and Samsung at 14nm to get pricing concessions which will make it even more difficult for Intel to compete. Additionally, Intel will have the added burden of the three idle fabs which brings utilization down to 50% (my guess since Intel was not “transparent” about it during analyst day). I’m really looking forward to the utilization conversation on the next earnings call. Mr. Smith has some explaining to do! Let’s see what kind of answer $15M+ in CFO compensation will get us. Since TSMC 20nm and 16nm use the same metal fabric the fabs are the same so expect a very high utilization rate.

    Also read: Should Intel Offer Foundry Services?

    Bottom line is that the Intel 14nm “Fill the Fab” foundry strategy is a paper tiger to appease Wall Street. At 10nm it may be a different story all together. If Intel does in fact deliver 10nm SoCs a year or two ahead of the foundries they may get business at the normal Intel price premium. But at 14nm it is simply not going to happen, no way, no how.

    I also question the business model where you allow your products to be manufactured by a direct competitor. It is a conflict of interest. It is a desperate business move. It is the reason why pure-play foundries exist. But these are desperate times with only one pure play foundry (TSMC) for leading edge SoC silicon. If GlobalFoundries and UMC had the capacity and were able to deliver wafers lockstep with TSMC, Samsung and Intel would not have a chance in the foundry business, absolutely.

    More Articles by Daniel Nenni…..

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    TSMC: 3D, 450mm, CoWoS and More

    TSMC: 3D, 450mm, CoWoS and More
    by Paul McLellan on 12-18-2013 at 4:29 pm
    Categories: Foundries, TSMC

    The first keynote at the Burlingame 3D conference was by Doug Yu of TSMC. Not surprisingly he was talking about 3D. In particular, TSMC has WLSI technology that they call CoWoS, which stands for chip-on-wafer-on-substrate which pretty much describes how it is built. This is the technology that Xilinx uses for its recently announced high end arrays which I already wrote about here.

    The basic driver, in Doug’s view, is that on-chip interconnect is not scaling with Moore’s Law and so alternative approaches are required. He didn’t talk about cost (the manufacturers rarely do but when they talk about higher performance and lower power and don’t mention cost then you have to know the news is not wonderful. At best 20nm is flat to 28nm cost wise).

    Another issue is that at 16nm FinFET it is not clear that everything we used to be able to integrate onto a chip, such as RF and analog, will still work. At least at acceptable cost. One obvious advantage of any sort of 3D chip is the ability to mix die from different processes, such as having a 28nm didital chip with 90nm RF/analog (what Doug calls “a ranch in the middle of Manhattan”) and move the 10um inductor off-chip. This saves chip area, cost and power.

    TSMC is looking at how to ramp this 3D technology fast to volume. The costs of CoWoS are still too high but there is not really any substitute for the type of yield learning that comes from building products at volume. TSMC sees their goal to grow from a chip foundry to a subsystem foundry, delivering integrated subsystems consisting of die from multiple processes integrated together using CoWoS. He thinks that there are at most 5 companies that could potentially be suppliers into this market.

    During questions he was asked about TSMC’s views on TSV holes. There are a number of ways of building TSVs. Via first means that the TSVs are created before the first layer of metal (I don’t think it is possible to do them before the transistors due to the high temperatures used in the FEOL, but I am certainly not a process expert). Via middle means that some metal is created and then the TSV is added and additional metal layers later to hook everything up. It is also possible to create the via from the backside of the wafer. The TSMC view is to do the TSVs as early as possible. Someone pointed out that you cannot use copper for the TSV if you do via first but Doug said that was not true and TSMC uses it today.

    Eventually TSMC will scale all this to 450mm but it is too hard to move to 450mm at the same time as a node-change, so that 450mm will first be introduced on a node that is already running at volume. 28nm is my guess. But for wafer scale integration like CoWoS then 450mm is ideal since the costs are lower and they are not trying to get critical features to yield right out at the edge of the wafer where everything is more difficult.

    The general impression from the keynotes at 3D ASIP was that:

    • 3D (which really means 2.5D and memory stacks for now) is real and 2014 will start to ramp
    • costs will come down with yield learning once a few million units have been built and shipped
    • driver will be high end initially (HPC, networking) not mobile, but mobile is the dream to really drive volume
    • the biggest problem is, surprisingly, not the TSVs but bond of the wafer onto a substrate for thinning, and then debonding the thin wafer afterwards and all the handling
    • interposers will have more than wires on. Once costs come down it makes no sense to leave the I/Os on a 20nm die instead of putting them on the interposers (they don’t really shrink anyway). Also power transistors, capacitors etc. If only wires, organic substrates will probably win.
    • component cost of a 3D chip will not be less than multiple components but the saving at the system level might be very large

    More articles by Paul McLellan…

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    QCOM delivers first TSMC 20nm mobile chips!

    QCOM delivers first TSMC 20nm mobile chips!
    by Daniel Nenni on 11-21-2013 at 3:00 pm
    Categories: Foundries, Intel Foundry, TSMC

    QCOM is now sampling the TSMC 20nm version of its market dominating Gobi LTE modem. The announcement also included a new turbo charged version of their 28nm Snapdragon 800 SoC with a Krait 450 quad core CPU and Adrino 420 GPU. Given the comparable benchmarks between the Intel 22nm SoC and the 28nm SoCs from Apple and QCOM, the new 20nm mobile products from the top fabless semiconductor companies will be well beyond Intel’s 22nm reach, absolutely.

    The question is: When will Intel have a competitive 14nm SoC? The answer will hopefully come today at the Intel Analyst conference so stay tuned to SemiWiki. I will compare the conference info with what I have heard and see how they match up. Spoiler alert: Production Intel 14nm SoCs will not arrive until 2015, believe it.

    TSMC’s 20nm process technology can provide 30 percent higher speed, 1.9 times the density, or 25 percent less power than its 28nm technology. The advanced 20nm technology demonstrates double digit 112Mb SRAM yield. The high performance device equipped with second generation gate-last HKMG and third generation Silicon Germanium (SiGe) strain technology. By leveraging the experience of 28nm technology, TSMC’s 20nm process can further optimize Backend-of Line (BEOL) technology options and deep collaboration with customers to continue the Moores’ Law shrinking path. Technology and design innovation keep production costs in check.

    The new QCOM Krait 450 quad-core SoC is the first mobile CPU capable of running at speeds of up to 2.5GHz per core with a memory bandwidth of 25.6GB/s which will significantly increase the speed of running apps and browsing the internet. According to QCOM it is also capable of delivering Ultra HD (4K) resolution video, images, and graphics to mobile devices and HDTVs via their new Adreno graphics engine (the Adreno 420 GPU claims a 40% graphics boost over the Snapdragon 800). QCOM also claims to have integrated hardware accelerated image stabilization, which would be an industry first. The quad core processors are still 32-bit which was a bit of a disappointment for me. If anyone can push Android to 64-bit it is QCOM. As it turns out, Apple really did pull a rabbit out of the hat with their 64-bit ARM based A7 SoC for the iPhone5s which I have and am thoroughly enjoying!

    “Using a smartphone or tablet powered by Snapdragon 805 processor is like having an UltraHD home theater in your pocket, with 4K video, imaging and graphics, all built for mobile,” said Murthy Renduchintala, executive vice president, Qualcomm Technologies, Inc., and co-president, QCT. “We’re delivering the mobile industry’s first truly end-to-end Ultra HD solution, and coupled with our industry leading Gobi LTE modems and RF transceivers, streaming and watching content at 4K resolution will finally be possible.”

    The FinFET version of Snapdragon and Gobi LTE modems are expected to sample one year from now with a 20% performance boost or a 35% power savings from the silicon alone. I also expect it will have a 64-bit ARM based architecture for greater throughput. Apple’s next A8 SoC (iPhone6) is also TSMC 20nm which will mark the first time Apple has competitive silicon with competing tablets and smartphones. Apple’s A7, which just came out, is old school 28nm and last year’s A6 was 32nm. Exciting times in the fabless semiconductor ecosystem, absolutely!

    See the Qualcomm presentation HERE.

    More Articles by Daniel Nenni…..

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    Xilinx Begins Shipping TSMC 20nm FPGAs!

    Xilinx Begins Shipping TSMC 20nm FPGAs!
    by Daniel Nenni on 11-11-2013 at 10:00 am
    Categories: FPGA, TSMC, Xilinx

    Xilinx just announced the shipment of the first TSMC based 20 nm FPGAs, beating Altera to the punch yet again. Xilinx was also the first to ship TSMC 28nm FPGAs and will undoubtedly beat Altera to 14nm which could be the knockout punch we have all been waiting for. The Xilinx UltraScale is a new family of FPGAs that will use 20nm and 16nm processes with 20nm samples available just in time for Christmas! Ho ho ho…

    “This announcement underscores our first-to-market leadership commitment of delivering high-performance FPGAs,” said Victor Peng, senior vice president and general manager of products at Xilinx. “The next generation starts now with the shipment of our new UltraScale devices, building upon the tremendous momentum we have established with our 7 series.”

    “The delivery of UltraScale devices on TSMC’s 20nm process technology marks a new juncture for the semiconductor industry,” said TSMC vice president of R&D, Dr. Y.J. Mii. “We are happy to see Xilinx continue to break new ground and deliver 20nm silicon to its customers.”

    In 2012 the FPGA market was about a $4.5 billion business. Xilinx has about 50% market share at $2.2 billion. Altera is not far behind at $1.8 billion. Being the first to silicon is key in the FPGA world as it not only builds market share, it also builds trust that Xilinx can continue to deliver leading edge products.

    Xilinx and longtime manufacturing partner UMC were about one year late at 40nm which allowed Altera and manufacturing partner TSMC to gain significant FPGA market share. Xilinx then switched to TSMC at 28nm and the race with Altera on a level manufacturing playing field began. Clearly Xilinx won 28nm with not only first silicon shipped but also first to 3D IC technology.

    One of the big questions I see around the internet is: “Why did Altera really switch to Intel for 14nm?” Simple: Because Altera cannot beat Xilinx to market on a level manufacturing playing field. Even though Altera is a long time TSMC partner, TSMC does not play favorites and delivered technology to both Altera and Xilinx in a uniform manner.

    As previously reported, Intel 14nm is late. Word from Altera is that they won’t start taping out 14nm designs until Q4 2014. Xilinx, on the other hand, is taping out 16nm designs early in Q1 2014. Intel is not talking in detail about the speed and density of 14nm in regards to their foundry business so I have no idea how competitive Altera will be against Xilinx at 14nm. But Altera being a year or more late to market is 40nm all over again.

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