I have previously published analysis’ converting leading edge logic processes to “standard nodes” and comparing standard nodes by company and time. Recently updated details on the 7nm process node have become available and in this article, I will revisit the standard node calculations and trends.
Designing at 7nm with ARM, MediaTek, Renesas, Cadence and TSMC
The bleeding edge of SoC design was on full display last month at DAC in Austin as I listened to a panel session where members talked about their specific experiences so far designing with the 7nm process node. Jim Hogan was the moderator and the panel quickly got into what their respective companies are doing with 7nm technology already. Earlier this year we heard about the first 10nm chip being used for the Qualcomm Snapdragon 835 chip, so I was quite interested to here what the next smaller node at 7nm was going to bring us.
Continue reading “Designing at 7nm with ARM, MediaTek, Renesas, Cadence and TSMC”
TSMC Unveils More Details of Automotive Design Enablement Platform
At this year’s Design Automation Conference (DAC), TSMC unveiled more details about the design enablement platforms that were introduced at their 23[SUP]rd[/SUP] annual TSMC Technology Symposium earlier this year. I attended a presentation on TSMC’s Automotive Enablement Platform held at the Cadence Theater where TSMC’s Tom Quan gave a great overview of their status. Before diving into automotive, as a quick review, Tom updated us on all four of the segments covered by their enablement platforms, those being Mobile, High Performance Computing, Automotive and Internet of Things. Compound annual growth rate of wafer revenue from each of these areas was 7%, 10%, 12% and 25% respectively. Mobile consumes wafers from 28HPC+, 16FFC, 10nm and is now seeing some 7nm starts. HPC is in production at 16FF+ with newer designs targeting 7nm. IoT has the broadest breadth of wafer usage including 90nm, 55ULP, 40ULP, and 28HPC+ with 7nm ready for design starts.
Automotive, the subject of Tom’s presentation, is ready for design starts using 16FFC process. Tom started his presentation by giving a quick overview of the different types of ICs now being used in the automotive space. The biggest driver of platform complexity comes from infotainment and the growing space of ADAS (Advanced Driver Assistance Services). ADAS alone has several categories of applications and associated ICs including using vision, radar and audio capabilities for detection, avoidance, varying degrees of autonomous driving features, voice recognition, natural language interfaces, vision enhancement, and the list goes on. Overlaid on the traditional areas of power-train, engine control, chassis and suspension, communications and infotainment are now safety and security. All these functions are represented by more than 40 customers who have done over 600 tape-outs to TSMC with more than 1 million 12 inch equivalent wafers worth of ICs being shipped.
TSMC has put a tremendous amount of work into capturing this market building upon their successful Open Innovation Platform, better known to many of us as TSMC OIP. The whole idea of OIP is to bring together the thinking of customers and partners to enable an ecosystem that speeds time-to-market and ultimately shortening time-to-money for all involved. TSMC OIP boasts over 16 years of collaboration with more than 100 ecosystem partners and spans 13 technology generations that includes over 14,000 IPs, 8200+ tech files and 270 PDKs for 90+ EDA tools. The enablement platforms build on this foundational work ensuring that all of the right building blocks and tools are in place to enable designs in a given end market – in this case automotive.
As an example, and since TSMC was presenting at the Cadence Theater, we can look at the collaboration between TSMC and Cadence. Their collaboration in automotive started in 2015 with a focus on identifying needs and solutions to ensure conformance with the two main standards in this space which are AEC-Q100 and ISO-26262. Functional safety was a key area of collaboration and Cadence and TSMC started by training their engineers on functional safety requirements for the automotive space. Within the last two years, Cadence alone has trained over 100 engineers, many of which have been officially certified by an outside agency. Together, TSMC and Cadence have engaged with customers doing automotive ICs and IPs and as a result, Cadence developed a portfolio of interface IPs in TSMC’s 16FFC process supporting those customers. Many of these IP already meet AEC-Q100 requirements for Grade 2 temp range and Cadence has committed to qualify their controller IPs to be ISO 26262 ASIL-ready.
With respect to design tools and flows, in the second half of 2016, TSMC and Cadence worked to define a methodology for fault injection simulation and functional safety campaign management. In that time frame Cadence gained ISO 26262 tool compliance on 30+ tools in analog-mixed-signal, digital verification and front-end digital implementation and signoff flows. This work has also now prompted the collaboration to work on ‘reliability-centric’ design flows for 16nm and below including features such as aging simulations, self-heating, electro-migration analysis, FIT (failures in time) rate calculations and yield simulations.
TSMC wraps this effort up under another TSMC umbrella called TSMC9000. TSMC9000 and associated programs for TSMC Library and IP are quality management programs that aim to provide customers with a consistent, simple way to review a set of minimum quality requirements for libraries and IP designed for TSMC process technologies. The TSMC9000 team monitors ongoing IP quality and their requirements are documented and constantly revised to keep IP quality requirements up-to-date. TSMC IP Alliance members submit required data to TSMC for assessments. Assessment results are posted online so that customers can see the results and scores and understand the IP confidence level and/or risk of using a given IP. Having these assessment results readily available can significantly shorten design lead time and lower total cost of ownership for automotive IC and systems providers.
TSMC9000A (A for automotive) is based on requirements from ISO 26262 and AEC-Q100 to cover IP quality, reliability and safety assessment. It includes automotive grade IP at the 16FFC node targeted to automotive ADAS and Infotainment applications. Most of the current automotive IP has completed technology qualification for AEC-Q100 grade 1 up to 150[SUP]0[/SUP] C (Tj) and have been re-qualified with automotive-specific DRC/DRM decks. These IP are also ISO 26262 ASIL ready including safety manuals, FMEA/FMEDA, and ASIL B(D) certification.
In summary, TSMC’s automotive design enablement platform on 16FFC is ready to go. It will be interesting to see by the next DAC how far this platform has progressed both in terms of content and usage as the world progresses towards autonomous self-driving vehicles.
See also:
TSMC Design Platforms Driving Next-Gen Applications
TSMC @ #54DAC!
TSMC has been an ardent supporter of DAC for the last 18 years which has brought in the other foundries because, as the industry leader, wherever TSMC goes the other foundries naturally follow. The exception of course is Intel Custom Foundry because they march to the beat of a different drummer, if you know what I mean. The CoFluent group of Intel does exhibit at DAC, yes Intel became an EDA company with the purchase of French ESL company CoFluent in 2011. I’m not sure who their customers are but probably not the growing number of companies that compete with Intel due to their acquisitions but I digress…
This year TSMC has some notable speakers that you may want to catch:
TECHNICAL PANEL
Minimizing IC Power Consumption: Top Down or Bottom up Design Methodology. What is the Starting Point?
Moderator – John Blyler – Electronic Design Mag.
Aditya Mukherjee – Microsoft
Tim Saxe – QuickLogic Corp.
Abhishek Ranjan – Mentor, A Siemens Business
Ronald Martino – NXP Semiconductors
Lluis Paris – TSMC
Jon Adams – ON Semiconductor
Lluis Paris is Director of World Wide IP Alliance at TSMC and a recognized IP expert, in fact he is the top IP person I know and that is saying a lot because I know many. Lluis came to TSMC from the Emerging Memory Technology acquisition where he was COO. Not only does Lluis have a PhD in Microelectronics, he also has an MBA so he is definitely worth your time. I also know Tim Saxe from my Zycad and GateField FPGA days. Tim has a PhD in Electrical Engineering from Stanford and is a straight shooter with YEARS and YEARS of experience so he is definitely worth listening to.
The panel is on Monday at 3:30pm in the Convention Center, Ballroom G and I will be at this one. Lluis is also participating in the Mentor Booth Panel on the Impact of ISO 26262 on the fabless ecosystem on Tuesday at 5pm.
Tom Quan is also one of my favorite TSMC presenters. Tom has been at TSMC for ten years and before that he was an EDA staple. Prior to EDA, he was a Design Engineer at Intel. Tom is an AMS expert so that is where you can usually find him. This year he is quite busy:
LUNCH PANELS
Cadence: High Performance Digital Design at 7nm
Tuesday 12:00pm at the Convention Center – Ballroom B & C
Synopsys: Custom Compiler in 7nm
Tuesday 11:30am Hilton Hotel, 6th Floor, Austin Grand Ballroom H
BOOTH PRESENTATIONS
Synopsys: Design Enablement for HPC, Mobile, IoT and Automotive Applications
Monday 2:00pm
Cadence: TSMC Automotive Design Enablement Platform
Tom Quan Tuesday 2:00pm, Chek-San Leong Tuesday at 4:00, and Captain Liu Wednesday 1:30pm.
Captain Liu spent his career in EDA (Springsoft/Synopsys) before coming to TSMC two years ago. Captain is also busy at DAC:
BOOTH PRESENTATIONS
Cadence: TSMC-Cadence Collaboration for Digital Design Enablement at 7nm Monday at 11:30am and 1pm.
Synopsys: Design Enablement for HPC, Mobile, IoT and Automotive Applications Tuesday at 1:30pm.
ANSYS: Tool Flow Verification Monday at 2:45pm.
My good friend Willy Chen will be on the Synopsys breakfast panel: ARM, Synopsys and TSMC collaboration to enable high performance design with the latest processors and FinFET processes, including 7nm Monday morning. I will be at that one as well.
Last but not least Libby Aston and Chek-San Leong will be presenting Design Enablement for HPC, Mobile, IoT and Automotive Applicationsat the Chip Estimate booth on Tuesday and Wednesday at 1:30pm respectively.
You can see all of the DAC events HERE.
Please notice that TSMC 7nm is all over DAC this year meaning that we will see production chips in 2018, absolutely! Exciting times, I hope to see you there!
Live from the TSMC Earnings Call!
Last week I was invited to attend the TSMC earnings call at the Shangri-la Hotel in Taipei which was QUITE the experience. I generally listen in on the calls and/or read the transcripts but this was the first one I attended live. I didn’t really know what to expect but I certainly did NOT expect something out of Hollywood. Seriously, there were photographers everywhere taking hundreds of pictures. I was sitting front row center and as soon as the TSMC executives sat down there was a rush of paparazzi and the clicking sounds were deafening. It was a clear reminder of how important TSMC is in Taiwan, and the rest of the world for that matter.
The most interesting news for the day was that 10nm is progressing as planned with HVM in the second half of this year. In fact, 10nm should account for 10% of TSMC wafer revenue this year (Apple). There had been rumors that foundry 10nm was in trouble (fake news) but clearly that is not the case for TSMC. In fact, according to C. C. Wei:
Although N10 technology is very challenging, the yield learning progression has been the fastest as compared to the previous node such as the 20- and 16-nanometer. Our current N10 yield progress is slightly ahead of schedule. The ramp of N10 will be very fast in the second half of this year.
C.C. also gave an encouraging 7nm update:
TSMC N7 will enter risk production in second quarter this year. So far, we have more than 30 customers actively engaged in N7. And we expect about 15 tape-outs in this year with volume production in 2018. In just 1 year after our launch of N7, we plan to introduce N7+ in 2018. N7+ will leverage EUV technology for a few critical layers to save more immersion layers. In addition to process simplification, our N7+ provides better transistor performance by about 10% and reduces the chip size by up to 10% when compared with the N7. High volume production of N7+ is expected in second half 2018 — I’m sorry, in second half of 2019. Right now, our focus on EUV include power source stability, pellicle for EUV mask and stability of the photoresist. We continue to work with ASML to improve the tool productivity so that it can be ready for mass production on schedule.
And last but not least 5nm:
We have been working with major customers to define 5-nanometer specs and to develop technology to support customers’ risk production schedule in second quarter 2019, with volume ramp in 2020. Functional SRAM in our test vehicle has already been established. We plan to use more layers of EUV in N5 as compared to N7+.
The other interesting technology update was InFO:
First, we expect InFO revenue in 2017 will be about USD 500 million. Now we are engaging with multiple customers to develop next-generation InFO technology for smartphone application for their 2018, 2019 models. We are also developing various InFO technologies to extend the application into high-performance computing area, such as InFO on substrate, and we call it InFOoS; and InFO with memory on substrate, InFO-MS. These technologies will be ready by third quarter this year or first quarter next year.
If I remember correctly, InFO contributed $100M last year (Apple) so this is great progress. By the way, now that I have seen the facial expressions that go with the voices during the Q&A I can tell you that C.C. has a very quick wit. I had pity for the analysts who tried to trip up C.C. and get inappropriate responses from him.
Mark Lui talked about ubiquitous computing and AI which reminded me why TSMC is in the dominant position they are today. As a pure-play foundry TSMC makes chips for all applications and devices. Ubiquitous says that computing can appear anytime and anywhere meaning all of those mobile devices TSMC has enabled over the past 30 years will continue to evolve making the TSMC ecosystem worth its weight in silicon.
I also have a new perspective on the analysts that participate in the Q&A after sitting amongst them. I have no idea how much they get paid for what they do but I’m pretty sure it is too much.
Here is my favorite answer for Q1 2017:
Michael Chou Deutsche Bank AG, Research Division – Semiconductor Analyst Okay, the next question, sir, management mentioned the log scale comparison versus Intel, I think, the 2014, right? So since Intel came out to say that their technology seems to be 3 year ahead of the other competitor, including your company, so do you have any comment on your minimum metal pitch and the gate pitch comparison versus Intel? Or do you have any comment for your 5-nanometer versus Intel 10-nanometer, potential 7-nanometer?
C. C. Wei Taiwan Semiconductor Manufacturing Company Limited – Co-CEO and President Well, that’s a tough question. I think every company, right now, they have their own philosophy developing the next generations of technology. As I reported in the foundry, we work with our customer to define the specs that can fit their product well. So the minimum pitch to define the technology node, we are compatible to the market. But the most important is that we are offering the best solution to our customers’ product roadmap. And that’s what we care for. So I don’t compare that really what is the minimum pitch to define the technology node.
Absolutely!
A PDF of the meeting is HERE. The presentation materials are HERE. I have pages of notes from the event and the trip in general so lets talk more in the comments section and make these analysts green with envy!
TSMC Design Enablement Update
A couple of recent semiwiki articles reviewed highlights of the annual TSMC Technical Symposium recently held in Santa Clara (links here, here, and here). One of the captivating sessions at every symposium is the status of the Design Enablement for emerging technologies, presented at this year’s event by Suk Lee, Senior Director at TSMC. In the broadest sense, design enablement refers to both EDA tools and design IP, developed specifically for the new process node.
TSMC focuses on early engagement with EDA vendors, to ensure the requisite tool features for a new process node are available and qualified, on a schedule that supports “early adopter” customers. As the prior semiwiki articles have mentioned, N10 tapeouts will be ramping quickly in 2017, with N12FFC and N7 soon to follow. So, it was no surprise that the EDA tool status that Suk presented for these nodes was green, usually for multiple EDA vendors (e.g., 3 or 4).
The unique part of Suk’s presentation is the description of key EDA tool requirements presented by the new process node. These offer insights into the additional complexities and design characteristics introduced. Here are some of the new features that struck me as particularly interesting.
stacked vias and via pillars
There are two characteristics of each new process node that are always troublesome for designers, and for the optimization algorithms applied during physical implementation. The scaling of metal and via pitches (for the lowest metal layers) results in increased sheet and via resistance. Correspondingly, this scaling also exacerbates reliability concerns due to electromigration — this issue is magnified due to the increased local current density associated with FinFET logic circuits.
SoC designs at these new nodes need an efficient method to utilize the upper level layers in the overall metallization stack, for reduced RC delay and/or improved electromigration robustness. Suk presented two options that are being recommended for N7 — stacked vias and via pillars. Design rules enabling stacked vias are leveraged by the TSMC Mobile platform, while the expectation is that the High-Performance Computing (HPC) platform designs will need to regularly use via pillars. A via pillar is depicted in the figure below.
Suk highlighted some of the unique EDA tool algorithms needed, to support the prevalent use of via pillars:
- physical synthesis, clocktree synthesis, APR
Physical implementation algorithms need to assess where via pillars are needed — there is a significant interconnect timing improvement versus route track blockage tradeoff assessment required.
- parasitic extraction, static timing analysis, EM, and I*R
The via pillar is a unique geometry. RC extraction tools need to translate this topology into a suitable model for subsequent electrical analysis (EM, I*R), specifically how the current will spread throughout the pillar. EDA vendors have addressed this via design insertion and analysis requirement for N7 — this is fully green.
One area that has me curious that Suk didn’t mention is the yield impact of using via pillars. Commonly, yield enhancement algorithms are exercised near the end of physical implementation, often by attempting to add redundant vias where feasible — perhaps, a via pillar insertion strategy will evolve as a new DFM/DFY option.
“cut metal” masks and coloring
Advanced process nodes have replaced traditional metal interconnect lithographic patterning with spacer-based mandrels and cuts, to realize more aggressive pitch dimensions. The drawn metal layout shapes are translated into drastically different mask implementations, involving the addition of: mandrel shapes (for spacer-based damascene metal etching); “cut masks”; and, metal/cut decomposition color assignment (associated with multi-patterning and successive litho-etch steps). There are optimizations available to reduce the need for multi-patterning of cuts, by adjusting the cut spacing through the addition of metal extensions — the figure below illustrates a simple example.
(From: “ILP-based co-optimization of cut mask layout, dummy fill, and timing for sub-14nm BEOL technology”, Han, et al., Proc. SPIE, October, 2015. Note the metal extensions added to align cuts.)
TSMC has worked with EDA vendors to optimize metal and cut mask generation, and multi-patterning decomposition. Flows impacted include physical implementation, LVS, and extraction. Suk’s presentation also briefly mentions that ECO flows with cut metal and metal extensions needed to be updated, as well.
dual pitch BEOL
At the symposium, TSMC introduced an aggressive technology roadmap, including the new N12FFC offering. This technology is intended to offer a migration path for existing 16FF+/16FFC designs.
N12FFC includes an improved metal pitch on lower levels, as compared to N16. Logic blocks would be re-implemented with a 6T cell library, from TSMC’s Foundation IP for N12FFC. Other hard IP would be re-characterized, without new layout. As a result, EDA vendors need to support dual-pitch back-end-of-line (BEOL) IP pin and routing implementations, integrating both new 12FFC and existing 16FFC blocks.
Suk highlighted that the Design Enablement team at TSMC is also introducing technology model support (and qualified EDA tools) to address the reliability challenges of new process nodes, especially the more stringent targets of automotive applications — e.g., advanced electromigration analysis rules, advanced (self-heat) thermal models for local die temperature calculations, device parameter end-of-life drift due to BTI and HCI mechanisms.
The close collaboration between TSMC and the EDA tool developers is fundamental to early customer adoption for emerging technologies. Each new node introduces physical implementation and electrical analysis challenges to conquer. It will be interesting to see what new EDA tool and flow capabilities the N5 process node will require.
-chipguy
14nm 16nm 10nm and 7nm – What we know now
Last week Intel held a manufacturing day where they revealed a lot of information about their 10nm process for the first time and information on competitor processes continues to slowly come out as well. I thought it would be useful to summarize what we know now, especially since some of what Intel announced was different than what I previously forecast.
Continue reading “14nm 16nm 10nm and 7nm – What we know now”
Integrated Photonics Accelerates with Entrance of TSMC and TowerJazz Foundries
I’m writing this from the Boston airport on my way home from four straight weeks of PIC (photonic integrated circuit) related travel. It’s been a grueling but very rewarding four weeks and the big take away from this month is that there are now many more signs in the market that integrated photonics is reaching a real tipping point.
I started off March by traveling to Brussels, Belgium to attend the PIC International Conference. This was PIC International’s second year and attendance grew from 440 attendees last year to over 550 this year. This was echoed at the Optical Fiber Conference held in Los Angeles which boasted 14,500 attendees and over 663 exhibitors. The conference was packed with talks about how the industry is girding for the explosive data growth expected to be driven by IoT and 5G cellular. Another key indicator of growing momentum was a 30% increase in attendance of conference short courses meant to educate professionals on the technical aspects of photonics.
The real buzz however, came with several noteworthy news items in March. Among them was a press release by Luxtera where they announced they will be offering a high performance silicon photonics platform with TSMC. The new platform will enable system-on-chip integration of optical interconnect with CMOS logic and will be leverage TSMC’s 7nm CMOS technology. The Luxtera platform is targeting next-generation silicon photonics solutions to deliver 100G-per-lane optical interconnects, starting with 100GBase-DR and 400GBase-DR4 transceivers which they anticipate launching in 2018.
This was promptly followed by a press release from TowerJazz where they too announced they will be providing a new Silicon Photonics process targeting the Optical Transceiver Electronics market. The TowerJazz SiPho process will be based on their SiGe BiCMOS process. When you start seeing production foundries like TSMC, TowerJazz and GLOBAL FOUNDRIES (as announced late last year) getting into the market you know the significant volumes are on their way. This is big!
And lastly, of note was an offer was made by IDT to purchase GigPeak for $250M. GigPeak offers optical interfaces for communications, data centers and military and avionic modules. GigPeak had record profits for its fourth quarter and fiscal 2016 with shipments of its 40 Gbps QSFP+ and 100Gbps QSFP28 ICs for active optical cables (AOCs) and optical transceiver modules into data center customers. The company is also currently sampling driver and trans-impedance amplifier (TIA) ICs for 200 Gbit/s short-reach and long-reach PAM4 Ethernet applications.
The second week of my travels was spent on the east coast of the U.S. traveling up and down the I-90 corridor. One of the most interesting observations of that week was the uptake in the number of integrated photonics projects coming from commercial companies versus past activity which was primarily driven by universities and R&D labs. This was echoed by Twan Korthorst, CEO of PhoeniX Software, where he presented a graph at the PIC International Conference showing a shift of new PhoeniX users coming from commercial companies as opposed to academia. On a side note, PhoeniX’s OptoDesigner tool won the EPIC Award at this year’s PIC International show in the design and test category. While good news for PhoeniX, the interesting part for the reader is that more than 6000 engineers cast ballots for this award. That’s a lot of people for a nascent industry. It also explains PhoeniX’s 45% CAGR for PIC tools over the last four years.
The final week of my travels was spent in Boston at the MIT campus where I attended an AIM Photonics sponsored meetings to road map requirements for the integrated photonics ecosystem. In many cases members were excited to see road map items being accelerated forward by industry.
One of the most interesting presentations was given by Microsoft where they presented on their integrated photonics work used in Time-of-Flight (ToF) cameras and sensors. These cameras give full 3D imaging information for applications such as facial recognition security features. ToF sensors are already in the iPhone 7 and could be applied to future laptops, phones, TVs and gaming consoles. Cameras with 3D depth capabilities can be applied to a wide variety of applications such as gaming, in-air gesturing and augmented reality.
Microsoft, Apple, Intel and Google are all working to bring this ToF technology to bear. Now that would represent some real volume.
This is just the beginning as engineers are barely scratching the surface of what can be done with integrated photonics. From long haul telecommunications, RF and microwave applications, WIFI networks and data center switches, to high volume applications in automotive, mobile devices, industrial sensing and medical and bio-sensing arenas, it’s time to start placing your bets. Hang on to your hats. It’s going to be a wild ride for the next decade!
See also:
– Luxtera and TSMC Collaborate on NexGen Silicon Photonics
– TowerJazz Announces Silicon Photonics Offering
– IDT Makes Offer on GigPeak
– PhoeniX Software Selected for PIC Design & Test Award
Shootout at 22nm!
For an industry that drives improvement at an exponential rate it is funny how often something old is new again. Intel went into high volume production on 22nm in 2011, and TSMC and Samsung have both had 20nm technologies in production for several years. And yet, recently we have seen renewed interest in 22nm. GLOBALFOUNDRIES has a 22nm FDSOI technology (22FDX) ramping now, at their recent technology forum TSMC announced a bulk 22nm technology 22ULP for 2017 production and this week Intel also announced a new 22nm FinFET technology 22FFL or 2017 production. Why the resurgence of interest in 22nm?
20nm/22nm is the last node where the industry primarily relied on planar bulk technology and is also the break point where multi-patterning starts to come in. At smaller dimensions’ leakage issues have driven the transition to fully depleted devices with FinFETs leading the way. FinFETs provide excellent drive current and a good scaling path with 16nm/14nm processes in high volume production, 10nm ramping and 7nm on the horizon. With each new node, the cost to manufacture a transistor has come down and Moore’s law has continued, but this has come at a high price. Design rules have been growing rapidly and the cost to design on these processes is so high that only the largest volume products can justify the necessary investment in development costs. With each new node, fewer products will be designed onto each new technology. One of the key emerging areas for the industry is IOT where the opportunity space is expected to be split between many lower volume products. The need for processes with lower design costs is obvious. IOT we will also need very low power, RF, analog and reasonable digital density. All of the three companies mentioned above are targeting this market with these new 22nm processes.
The key 22nm process objectives are low design cost, little or no multi-patterning, low power and the features needed for IOT and mobile.
GLOBALFOUNDRIES (GF) 22FDX
I have written about 22FDX previously here and here. 22FDX is based on fully depleted SOI (FDSOI) and offers the unique ability to use biasing to achieve multiple threshold voltages and dynamically scale performance. 22FDX offers the lowest operating voltage of any process I am aware of at 0.4 volts. Since power consumption is proportional to voltage squared, 22FDX should provide very low power operation. 22FDX offers 50% faster speed or 18% lower power than GLOBALFOUNDRIES 28nm process. 22FDX also offers excellent RF performance with NMOS FT/FMAX of 350/325GHz and PMOS FT/FMAX of 290/250GHz. This is likely far higher than either of the other 22nm processes, for example GF 14LPP FinFET process only achieves FMAX of ~150GHz. 22FDX is ramping up now.
TSMC 22ULP
Announced only a few weeks ago, 22ULP is due to ramp by the end of 2017. 22ULP is based on a bulk technology and TSMC claims the Ion/Ioff curve is identical to a “22nm FDSOI” technology. The operating voltage is 0.6 volts and the process is said to offer 15% higher performance or 35% lower leakage than TSMC’s 28nm process.
Intel 22FFL
Announced this week, 22FFL is due to ramp in Q4 of 2017. 22FFL is based on Intel’s 22nm FinFET process that has been in production since 2011. 22FFL offers HP transistor with performance similar to Intel’s 14++ process and low leakage transistors with >100x lower leakage, see figure 1. RF is supported although FinFET RF performance is likely not nearly as good as FDSOI due to higher parasitic capacitances.
Figure 1. 22FFL Performance.
Process comparison
All three company’s processes are targeted at lower design costs and meeting the needs of IOT types of applications. Table 1 compares some of the key process characteristics for the three processes.
border=”1″ align=”center”
|-
| style=”width: 156px” | Company
| style=”width: 65px; text-align: center” | GF
| style=”width: 66px; text-align: center” | TSMC
| style=”width: 60px; text-align: center” | Intel
|-
| style=”width: 156px” | Process name
| style=”width: 65px; text-align: center” | 22FDX
| style=”width: 66px; text-align: center” | 22ULP
| style=”width: 60px; text-align: center” | 22FFL
|-
| style=”width: 156px” | Process type
| style=”width: 65px; text-align: center” | FDSOI
| style=”width: 66px; text-align: center” | Bulk
| style=”width: 60px; text-align: center” | FinFET
|-
| style=”width: 156px” | CPP (nm)
| style=”width: 65px; text-align: center” | 90 est
| style=”width: 66px; text-align: center” | 105 est
| style=”width: 60px; text-align: center” | 108
|-
| style=”width: 156px” | MMP (nm)
| style=”width: 65px; text-align: center” | 78 est
| style=”width: 66px; text-align: center” | 80 est
| style=”width: 60px; text-align: center” | 90
|-
| style=”width: 156px” | Tracks
| style=”width: 65px; text-align: center” | 8
| style=”width: 66px; text-align: center” | 7
| style=”width: 60px; text-align: center” | 7
|-
| style=”width: 156px” | CPP x MMP x Track (nm2)
| style=”width: 65px; text-align: center” | 56,160
| style=”width: 66px; text-align: center” | 58,800
| style=”width: 60px; text-align: center” | 68,040
|-
| style=”width: 156px” | Vdd (volts)
| style=”width: 65px; text-align: center” | 0.4
| style=”width: 66px; text-align: center” | 0.6
| style=”width: 60px; text-align: center” | NA
|-
Table 1. Process comparison
Looking at the three processes the GF 22FDX process appears to likely have the densest logic (although we do not have exact numbers for GF and TSMC). 22FDX use 2 multi-patterning layers in the middle of line to drive tighter interconnect plus has the smallest projected contacted poly pitch. 22FDX will also likely have the best RF performance and active power consumption. On other performance and leakage metrics we don’t have enough data to draw any conclusions yet.
One critical factor in designing for any technology is the availability of IP. With TSMC’s 22ULP being a planar bulk shrink from 28nm they will likely have the richest IP offering providing the fastest deign path. At their manufacturing day Intel had a foundry panel including executives from Cadence, ARM and Synopsys and they are clearly working on that area but likely still playing catch up. I know GF is also putting a lot of emphasis on IP and the design environment but it isn’t clear to me how much traction they are getting.
Conclusion
Designers of IOT and other mobile devices now have three new 22nm processes to choose from. The three processes take very different approaches. GF’s 22FDX is the most radical departure from the main stream but also likely delivers the best density, RF and power performance. TSMC’s 22ULP bulk planar process can likely offer the richest IP environment. Intel’s 22FFL is an evolution of the 22GP process that is one of the highest yielding processes in Intel’s history and offers 14++ like performance with very low leakage transistors.
Intel Manufacturing Day: Nodes must die, but Moore’s Law lives!
Yesterday I attended Intel’s manufacturing day. This was the first manufacturing day Intel has held in three years and according to Intel their most in depth ever.
Nodes must die
I have written several articles comparing process technologies across the leading-edge logic producers – GLOBALFOUNDRIES, Intel, Samsung and TSMC. Comparing logic technologies to each other requires a metric for process density.
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