TSMC’s Reliability Ecosystem

TSMC’s Reliability Ecosystem
by Tom Dillinger on 04-06-2022 at 10:00 am

AC accelerated stress conditions

TSMC has established a leadership position among silicon foundries, based on three foundational principles:

  • breadth of technology support
  • innovation in technology development
  • collaboration with customers

Frequent SemiWiki readers have seen how these concepts have been applied to the fabrication and packaging technology roadmaps, which continue to advance at an amazing cadence.  Yet, sparse coverage has typically been given to TSMC’s focus on process and customer product reliability assessments – these principles are also fundamental to the reliability ecosystem at TSMC.

At the recent International Reliability Physics Symposium (IRPS 2022), Dr. Jun He, Vice-President of Corporate Quality and Reliability at TSMC, gave a compelling keynote presentation entitled:  “New Reliability Ecosystem: Maximizing Technology Value to Serve Diverse Markets”.  This article provides some of the highlights of his talk, including his emphasis on these principles.

Technology Offerings and Reliability Evaluation

The figures above highlight the diverse set of technologies that Dr. He’s reliability team needs to address.  The reliability stress test methods for these technologies vary greatly, from the operating voltage environment to unique electromechanical structures.

Dr. He indicated, “Technology qualification procedures need to be tailored toward the application.  Specifically, the evaluation of MEMS technologies necessitates unique approaches.  Consider the case of an ultrasound detector, where in its end use the detector is immersed in a unique medium.  Our reliability evaluation methods need to reflect that application environment.”

For more traditional microelectronic technologies, the reliability assessments focus on accelerating defect mechanisms, for both devices and interconnect:

  • hot carrier injection (HCI)
  • bias temperature instability (NBTI for pFETs, PBTI for nFETs)
  • time-dependent dielectric breakdown (TDDB)
  • electromigration (for interconnects and vias)

Note that these mechanisms are highly temperature-dependent.

As our understanding of the physics behind these mechanisms has improved, the approaches toward evaluating their impact to product application failure rates have also evolved.

Dr. He commented, “Existing JEDEC stress test standards are often based on mechanism acceleration using a DC Vmax voltage.  However, customer-based product qualification feedback did not align with our technology qualification data.  Typically, the technology-imposed operating environment restrictions were more conservative.”

This is of specific interest to high-performance computing (HPC) applications, seeking to employ boost operating modes at increased supply voltages (within thermal limits).

Dr. He continued, “We are adapting our qualification procedures to encompass a broader set of parameters.  We are incorporating AC tests, combining Vmax, frequency, and duty cycle variables.”

The nature of “AC recovery” in the NBTI/PBTI mechanism for device Vt shift has been recognized for some time, and is reflected in device aging models.  Dr. He added, “We are seeing similar recovery behavior for the TDDB defect mechanism.  We are aggressively pursuing reliability evaluation methods and models for AC TDDB, as well.”

The figure above illustrates the how the Vt shift due to BTI is a function of the duty cycle for the device input environment, as represented by the ratio of the AC-to-DC Vt difference.  The figure also highlights the newer introduction of a TDDB lifetime assessment for high-K gate dielectrics, as a function of input frequency and duty cycle.

Parenthetically, Dr. He acknowledged that end application product utilization can vary widely, and that AC reliability testing makes some usage assumptions.  He indicated that TSMC works with customer to establish appropriate margins for their operating environment.

Reliability Evaluation of New Device Types

TSMC has recently added resistive RAM (RRAM) and magneto-resistive RAM (MRAM) IP to their technology offerings.

The unique physical nature of the resistance change in the storage device for these technologies necessitates development of a corresponding reliability evaluation procedure, to establish retention and endurance specifications.  (For the MRAM technology, the external magnetic field immunity specification is also critical.)

For both these technologies, the magnitude and duration of the write current to the storage cell is a key design parameter.  The maximum write current is a crucial reliability factor.  For the MRAM example, a high write current through the magnetic tunnel junction to set/reset the orientation of the free magnetic layer in the storage cell degrades the tunnel barrier.

TSMC collaborates with customers to integrate write current limiting circuits within their designs to address the concern.  The figure below illustrates the write current limiter for the RRAM IP.

TSMC and Customer Collaboration Reliability Ecosystem

In addition to the RRAM and MRAM max write current design considerations, Dr. He shared other examples of customer collaborations, which is a key element of the reliability ecosystem.

Dr. He. shared the results of design discussions with customers to address magnetic immunity factors – the figure below illustrates cases where the design integrated a Hall effect sensor to measure the local magnetic field.  The feedback from the sensor can be used to trigger corrective actions in the write cycle.

The customer collaboration activities also extend beyond design for reliability (DFR) recommendations.  TSMC shares defect pareto data with customers.  Correspondingly, the TSMC DFR and design-for-testability (DFT) teams will partner with customers to incorporate key defect-oriented test screens into the production test flow.

Dr. He provided the example where block-specific test screens may be appropriate, as illustrated below.

Power management design approaches may be needed across the rest of the design to accommodate block-level test screens.

The figure below depicts the collaboration model, showing how customer reliability feedback is incorporated into both the test environment and as a driver for continuous improvement process (CIP) development to enhance the technology reliability.

Summary

At the recent IRPS, TSMC presented their reliability ecosystem, encompassing:

  • developing unique reliability programs across a wide breadth of technologies (e.g., MEMS)
  • developing new reliability methods for emerging technologies (e.g., RRAM, MRAM)
  • sharing design recommendations with customers to enhance final product reliability
  • collaborating closely with customers on DFR issues, and integrating customer feedback into DFT screening procedures and continuous improvement process focus

Reflecting upon Dr. He’s presentation, it is no surprise that these reliability ecosystem initiatives are consistent with TSMC’s overall principles.

-chipguy

Also read:

Self-Aligned Via Process Development for Beyond the 3nm Node

Technology Design Co-Optimization for STT-MRAM

Advanced 2.5D/3D Packaging Roadmap


The EUV Divide and Intel Foundry Services

The EUV Divide and Intel Foundry Services
by Scotten Jones on 03-23-2022 at 10:00 am

Intel IDM 2.0 Process Roadmap
The EUV Divide

I was recently updating an analysis I did last year that looked at EUV system supply and demand, while doing this I started thinking about Intel and their Fab portfolio.

If you look at Intel’s history as a microprocessor manufacturer, they are typically ramping up their newest process node (n), in volume production on their previous node (n-1) and ramping down the node before that (n-2 node). They don’t typically keep older nodes in production, for example, last year 10nm was n, 14nm was n-1 and 22nm was n-2. Intel had some 32nm capacity in Fab 11X but that has now been converted to a packaging Fab. This contrasts with someone like TSMC that built their first 130nm – 300mm fab in 2001 and is still running it plus their 90nm, 65nm, 40nm and 28nm fabs as well.

By the end of 2022 Intel should be ramping up their 4nm node, then in 2023 their 3nm node, and in 2024 their 20A (2nm) and 18A (1.8nm) nodes should ramp up. All of those are EUV based nodes and it would seem reasonable that by the end of 2024 Intel would have little use for non-EUV based processes for microprocessor production since their 7nm/10nm non-EUV nodes would be n-4/n-5 depending on how you treat 10nm/7nm.

If I look at Intel’s current and planned Fab portfolio, there are EUV capable fabs and older fabs that are unlikely to ever be used for EUV, in fact EUV tools require an overhead crane and many of Intel’s older fabs would likely require significant structural modifications to accommodate this, plus Intel is building 9 EUV based production fabs.

The following is a site by site look at Intel’s fabs:

  • New Mexico – Fab 11X phases 1 and 2 are Intel’s oldest production fabs and they are being converted to packaging Fabs. 11X-3D may continue to operate for 3D Xpoint. Intel recently discussed two more generations of 3D Xpoint and this is currently the only place to make it.
  • Oregon – Fab D1X phases 1, 2 and 3 now lead all of intel’s EUV based development and early production. Fabs D1C/25 and D1D are older development/production fabs that are unlikely to be converted to EUV and are currently being used for non-EUV production.
  • Arizona – Fabs 52 and 62 are EUV fabs under construction. Fab 42 is currently running non-EUV nodes but it was built as a EUV capable Fab and will likely be used for EUV someday. Fabs 12 and 32 are production fabs running non-EUV nodes and will likely never be converted to EUV.
  • Ireland – Fab 34 is an EUV fab under construction with equipment currently being moved in, this will likely be Intel’s first 4nm EUV node production site. Fabs 24 phases 1 and 2 are non-EUV production sites and will likely never be used for EUV (unless they get combined with Fab 34 at some point).
  • Israel – Fab 38 is an EUV fab under construction and will be a 4nm EUV node production site. Fabs 28 phases 1 and 2 are non-EUV node production and will likely never be used for EUV (unless they get combined with Fab 34 at some point).
  • Ohio – Silicon Heartland EUV based fabs 1 and 2 are in the planning stage.
  • Germany – Silicon Junction EUV based fabs 1 and 2 are in the planning stage.

In summary Intel is in various stages of running, building, or planning the following EUV based fabs, D1X phases 1, 2 and 3, Fabs 42, 52, and 62, Fab 34, Fab 38, Silicon heartland 1 and 2 and Silicon Junction 1 and 2. That is 3 development fabs/phases and 9 EUV based production fabs.

For non-EUV fabs still running, Intel has D1C/25, D1D, Fabs 12 and 32, Fab 24 phases 1 and 2, and Fab 28 phases 1 and 2. That is 8 non-EUV production Fabs. This really puts into perspective why Intel would want to get into the foundry business and support trailing edge processes. All these fabs can be used to produce any of Intel’s non EUV 10nm/7nm and larger processes plus likely with reasonable changes in equipment sets any of the processes they will be acquiring from the Tower acquisition.

Déjà vu all over again

Yogi Bera is famous for being humorously quotable and one of his famous quotes was “it is Déjà vu all over again”.

The last time Intel tried to get into the foundry business they failed to gain much traction. Foundry was still a second-class citizen at Intel, they didn’t have the design eco system and eventually exited the foundry business. One of the things that bothered me about Intel’s effort and in my opinion sent a message to foundry customers that foundry was second class was that Intel would develop a new process node, for example 32nm, they would introduce a high performance version for internal use and then a year later introduce the foundry (SOC) version.

Recently I saw an interview with Pat Gelsinger where he talked about 4nm being an internal process for Intel and then 3nm being the foundry version. 3nm is currently expected to come out approximately a year after 4nm. He then talked about 20A as an internal process and 18A as the foundry version. 18A is due to come out 6 to 9 months after 20A. I don’t think foundry customers will accept always being 6 to 12 months behind the leading edge and I think it sends the wrong message. He did say if a foundry customer really wanted to use 4nm they could, but he seemed to view 4nm and 20A as processes that should be tested internally before the next version is released more widely.

I do think Intel has an interesting opportunity. There is a shortage of foundry capacity at the trailing edge where Intel will likely be freeing up a lot of fab capacity and there is a shortage at the leading edge as well. In addition to that, there is a need for a second source at the leading edge. Samsung has a long history of over promising and under delivering on technology and yield. Companies like Qualcomm have repeatedly tried to work with Samsung, so they aren’t wholly dependent on TSMC and have been repeatedly forced back to TSMC. The latest example is the Qualcomm’s Snapdragon 8 gen 1 that is reported to have only 35% yield on Samsung’s 4nm node. If Intel can execute on their technology roadmap in a consistent basis with good yield, they can likely pick up a lot of second source and maybe even some primary source leading edge business particularly at Samsung’s expense. I could even see a company like Apple giving Intel some designs to strengthen their negotiating position with TSMC. I wouldn’t expect MediaTek, a Taiwan company located near TSMC, or AMD or NVDIA due to competitive concerns to work with Intel, but never say never.

EUV  shortage

As I mentioned at the outset it is a EUV supply and demand analysis I have been doing that triggered EUV gap ideas. As I outlined above Intel plans to build out and equip 9 EUV based Fabs. At the same time TSMC 5nm is widely believed to have ended 2021 at 120 thousand wafer per month capacity. TSMC has announced they expect to double the end of 2021 capacity on 5nm, by the end of 2024 and that is before the Arizona 5nm fab comes online. TSMC has talked about 3nm being an even bigger node than 5nm. TSMC has also started planning on a 4 phase 2nm fab with a second site in discussion. Samsung started using EUV for one layer on their 1z DRAM and then 5 layers on their 1a DRAM. Samsung is planning a new EUV based logic fab in Texas and is building out logic and DRAM capacity in Pyeongtaek. SK Hynix has started using EUV for DRAM, Micron has pulled in their DRAM EUV use from the delta to gamma generation and even Nanya is talking about using EUV for DRAM. This begs the question, will there be enough EUV tools available to support all these needs and my analysis is that there won’t.

In fact, I believe there will be demand for 20 more EUV tools than ASML can produce each of the next 3 years. To put that is perspective, ASML shipped 42 EUV systems in 2021 and is forecasting 55 system in 2022. Interestingly I saw a story today where Pat Gelsinger commented that he is personally talking to the CEO of ASML about system availability and admitted that EUV system availability will likely gate the ability to bring up all the new fabs.

I think another impact the EUV system shortage will drive is a different view of what layers to use EUV on. If a layer is currently done with multi-patterning more complex than double patterning EUV is generally cheaper. EUV also enables simpler design rules, more compact layouts, and potentially better performance. EUV will be even more important as the switch is made to horizontal nanosheets. I believe companies will be forced to prioritize EUV use to the layers where it has the most impact and continue to use multi-patterning for other layers.

Also Read

Intel Evolution of Transistor Innovation

Intel Discusses Scaling Innovations at IEDM

Intel 2022 Investor Meeting


TSMC Earnings – The Handoff from Mobile to HPC

TSMC Earnings – The Handoff from Mobile to HPC
by Doug O'Laughlin on 01-20-2022 at 10:00 am

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Hello! The most important semiconductor company in the world reported earnings last night. It’s been something of a tradition to post Taiwan Semiconductor Company (TSMC) earnings posts not behind my paywall, and I think that I’m going to continue that to kickoff each earnings season.

There are so many threads in the TSMC call that I want to talk about, but the big one that I think we will look back on 2022 for TSMC is that this is the year HPC will become the largest part of the business. Let’s expand.

TSMC’s current business mix

Smartphones and HPC are neck and neck in the largest buckets for TSMC, but HPC is growing faster. The reason for sluggish smartphone growth was laid out pretty well by TSMC, and that’s volume growth in smartphones has topped out.

Yes, I think — let me add. The global smartphone unit growth last year is about 6%. So some of the — you see some of the company smartphone revenue may grow, it could be due to the pricing. But we — our pricing strategy, as you understand, is strategic, not optimistic. So we’ll grow with the smartphone units in our business.

Well TSMC just guided for “high 20s” growth, and long-term growth of 15-20% CAGR. They additionally guided to an accelerating 2022, and strong sequential growth into Q1. Given that they think that their business will grow in-line smartphone units, the only logical growth driver is HPC. I did some pretty simple math to back out what the HPC segment should look like given their assumptions on growth.

Let me answer the platform question. In 2022, we expect the HPC and automotive to grow faster than the corporate average. IoT, similar. Smartphones close to the corporate average. That’s the platform growth.

I’m a bit more bearish on smartphones growing 20%+ unit growth so let’s say smartphones grow at 15% next year, and DCE / Other grows at 10% as well. I grew automotive at 50% and IoT at ~28% – and the result is that HPC revenue crosses over smartphones in 2022. I use HPC revenue as the plug to then hit the ~28% revenue number. It looks like this is the year HPC is finally larger than Smartphones at TSMC.

For the longest time, I have believed that the largest incremental dollar pool of revenue growth will be HPC. It’s nice to see it come true and TSMC confirms that this is their belief as well. I first wrote about when I suspected meaningful growth in the data center in 2022 after Facebook’s earnings. I got it confirmed shortly thereafter by AIchip’s results. I had a suspicion that data center would be strong, but hearing the largest fab in the world expect something akin to ~40%+ growth in this segment is pretty mind-boggling even to a huge bull like me.

Another point to the leadership of the data center going forward is that HPC is starting to adopt the smaller nodes faster than smartphones, which used to be the premier first adopters of TSMC’s newest node. In the past, HPC would adopt the newest node a year after smartphone, but now HPC is in the driver seat and will be adopting N3 at the same time smartphone is. Beyond just node adoption, I’m pretty bullish on data center exposed stocks like Marvell and Nvidia.

Speaking of Marvell and Nvidia one of the questions on the call was “how can you grow your revenue faster than your fabless customer’s expected revenue growth”. TSMC answered that they believe it’s pricing and share gains.

This is C.C. Wei. Actually, the growth in 2022 is all the above you just mentioned. It’s a share gain, it’s the pricing and also its a unit growth. Did I answer your question?

Part of this is that Intel is starting to outsource to TSMC and that foundry likely will grow faster than memory this year. But I have a hard time believing another obvious answer is that the fabless estimates are too low.

Given that TSMC just guided to accelerating revenue (25% 2021 growth to 28%+ 2022 growth) and has over 50% of global market share, I have a hard time believing that the industry is going to meaningfully decelerate while TSMC revenue explodes. The numbers don’t reconcile. And that is why I believe that the fabless companies’ revenue estimates are likely a bit too low. Also that their 9% industry growth number is likely too low. Getting the theme here?

I believe that 2022 is going to be another strong year, and that almost every fabless company’s numbers will be revised higher. Let’s turn next to the capex side of the equation.

TSMC Expects to Spend $40-44B on Capex

Not only was growing faster for longer a surprise but the $40-44b capex was a real shocker. For context, the most bullish estimate on the street was at ~$40 billion. The upside is now the new downside case. Given that WFE grew by ~40% last year, and TSMC grew capex by ~77% in 2021 over 2020, this is pretty meaningful growth. In absolute terms, they are adding more spending in 2022 than in 2021. But of course, this is a deceleration on a larger base.

I think that the preliminary read-through is that WFE is going to have yet another good year. I believe that WFE likely is more to the tune of 20% growth than to 10% growth. Speaking of 10% growth – this estimate by SEMI came out on January 11th called for 10% growth and after TSMC’s spending estimates it already seems like this will be false. 2 days and it’s already out of date! The true number is going to be higher.

As we discussed on the VLSI semicap comparison of numbers bottom-up to top-down, it seems like estimates need to move higher. I think this is great for semicap broadly (surprise!). If you’re a long-time reader of the substack, one of the core beliefs is that the rising capital intensity of making a semiconductor accretes to fabs and even more so to semicap companies (ASML, LRCX, AMAT, KLAC, TOELY, etc).

This is just another indication that the thesis is correct given that Capex is growing faster than revenue. Which brings me to an interesting question – how could TSMC ever support this kind of spending indefinitely? The answer is that they are either utterly wrong about their growth and are going to throw the entire market into overcapacity, or that demand is still being underestimated. I believe that it’s the latter, as I wrote in my cyclical to the secular thought experiment. I believe that TSMC believes this as well, and given how they are investing and guiding, I want to call this TSMC’s bold bet.

Growing for Longer – TSMC’s Bold Bet

A recurring theme of the analysts calls with TSMC is that every quarter analysts pepper management with “how can you maintain the margin with this investment?” and “you’re spending a lot on capex will this ever normalize?” questions. The answer that TSMC answers each quarter is somewhere along the lines of “We are going to grow trust us”. This first long-term guidance in a while is an indication of that.

We expect our long-term revenue to be between 15% and 20% CAGR over the next several years in U.S. dollar terms, of course, fueled by all 4 growth platform which are smartphone, HPC, IoT and automotive.

The staggering thing I want to point out to you is their 10-year revenue growth CAGR is 14%. That’s the kind of growth that got them to the largest fab in the industry, yet their long-term revenue guide is now actually a call that their revenue will accelerate on a larger base. It’s impossible for them to gain share at the rate they used to so the only answer is the entire industry must accelerate as well.

TSMC is probably one of the best management teams in the entire industry with the most credibility you can ask for. They are prudent, ROIC focused, conservative in their node shrinks yet aggressive in their capital spending. Simply put they do not miss. If they are investing in larger amounts for accelerating growth they believe will come, I am going to believe them.

This is the definition of long-term thinking and bold bets. They are pushing forward at an even faster pace at the peak of their dominance in order to ensure they continue to hold share. And everything is pointing to the diversity and strength of the entire semiconductor ecosystem, and I think that the answer is clear. The 2020s are going to be a better decade than the one before it for the entire semiconductor ecosystem.

Passing Price

I want to briefly mention the gross margin part of the equation. Every quarter there is a lot of hang wringing about the sustainability of the gross margin at TSMC. Last quarter analysts got really hung up on “51% or greater” long-term margins and asked in as many ways as possible if that margin was sustainable.

This quarter of course they put up 53% gross margin and now are guiding to “53% or greater” margin longer term. The bar of course has shifted higher. The right answer and framing around the gross margin sustainability debate are that TSMC really is one of the only games in town, and the demand for their capacity is intense. I mentioned briefly that TSMC can just pass price as much as they want in the Rising Tide of Semiconductor Costs and I think that will continue.

No matter how much capex spend is required and how much depreciation and amortization will grow as a part of TSMC’s cost, TSMC is simply not a price taker. They will raise prices and pass their costs onto their customers, and in this case, it seems like they are able to pass on more than just the cost they take. If they can maintain 53%+ margins against rising CoGs, this means that customers will be taking price raises on the chin. Because what other choice do they really have? Intel’s Foundry business is still more of an idea more than a meaningful business, and Samsung is growing but relatively small. TSMC will get the money that they are due.

There’s a lot more in the transcript itself, which I recommend reading if you have some time. TSMC continues to believe I think that the continued prepayments by their customers are another indication that the fabless companies get it as well. They want more capacity because their businesses are well but they are capacity constrained.

An interesting idea I had was that the capacity precommitments in order to secure capacity feels a bit like the ASML investment by INTC / TSMC. It’s clearly a greater good, there is really only one company that can achieve it, and it’s going to cost a lot of money. In order for the economics to work at TSMC will need a lot of money.

Anyways that’s it for today. I just wanted to cover these points for now, and I’ll be posting a lot more content like this but for the ~100s of other semiconductor companies that will be reporting in the next month. I just always love to start with the biggest and baddest first.

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Self-Aligned Via Process Development for Beyond the 3nm Node

Self-Aligned Via Process Development for Beyond the 3nm Node
by Tom Dillinger on 01-05-2022 at 6:00 am

TEM DoD

The further scaling of interconnect and via lithography for advanced nodes is challenged by the requirement to provide a process window that supports post-patterning critical dimension variations and mask overlay tolerances.  At the recent international Electron Devices Meeting (IEDM) in San Francisco, TSMC presented a research update on their process development activities to realize a “self-aligned via” (SAV) for upcoming nodes, with an interconnect + via flow that provides improved manufacturability.[1]  This article summarizes the highlights of their presentation.

Introduction

The manufacturability of vias needs to address multiple litho, electrical, and reliability measures:

  • tolerance to overlay variation (aka, “edge placement error”, or EPE)
  • consistency of via resistance
  • robustness of via-to-adjacent metal dielectric properties
    • leakage current
    • maximum applied voltage before breakdown (Vbd)
    • dielectric reliability, measured as time-dependent dielectric breakdown (TDDB)

and, of course,

  • exceptional yield

(Note that these issues are most severe for the scaling of lower level metals and vias, denoted as “Mx” in the figures in this article.)

The overlay positioning between a via and an adjacent metal line impacts the dielectric breakdown – both Vbd and TDDB.  The figure below illustrates the overlay versus dielectric breakdown issue of a conventional via, for a representative EPE.

A “self-aligned” via (with a unique dielectric to an adjacent metal line) would provide greater process latitude to address the challenges listed above.

TSMC SAV Process

There are two key steps to the TSMC SAV process flow – the deposition of a “blocking layer” on metal lines and the selective deposition of dielectric-on-dielectric.

  • self-assembled monolayer (SAM) deposition on metal

A unique process chemistry step deposits a monolayer of a blocking material on an exposed metal surface.  This process is based on the affinity of organic chemical chains suspended in a solution to the metal.  The molecular chains are adsorbed on the metal surface, and self-assemble into an organized domain.  As the molecules adsorb over time, they will nucleate into groups and grow until the metal surface is covered with a monolayer.  (The monolayer packs tightly due to the van der Waals forces, the weak net attractive electric force between neutral organic solids.)

This SAM monolayer will serve as a blocking material.  Its composition needs to withstand the thermal exposure of the next step – the selective dielectric deposition on oxide.

  • selective dielectric-on-dielectric (DoD) deposition

Advanced nodes have leveraged atomic layer deposition (ALD) steps for several generations.  A gas phase “pre-cursor” is introduced into the process chamber.  Due to chemisorption, a unique pre-cursor monolayer is deposited on the wafer surface.  The pre-cursor adheres to the surface, but not to itself – no successive pre-cursor layers are deposited.  The chamber is then purged of the excess pre-cursor, and a co-reagent is subsequently introduced.  The chemical reaction results in a final monolayer of the desired reaction product that remains on the surface, while the excess co-reagent and reaction by-products are pumped out.  The cycle can be repeated to deposit multiple “atomic” layers.  ALD has been widely adopted for the deposition of metal and thin-oxide dielectric materials. A key advantage of current ALD processes is they operate uniformly and conformally on the exposed wafer surface.

An active area of research is to provide selective area atomic layer deposition, where the pre-cursor only adheres to a specific material surface.  The goal is the pre-cursor adsorption is suppressed on specific areas – in this case, the SAM molecules on the metal.

TSMC explored a selective deposition chemical process, for dielectric-on-dielectric layer buildup.  The images in the figure below depict the process flow to raise a dielectric layer above the existing surface oxide.

The SAM blocking layer precludes the selective deposition on the exposed dielectric.  As mentioned earlier, the blocking layer must withstand exposure to the elevated temperature of the dielectric-on-dielectric selective deposition.  TSMC indicated that higher DoD process temperatures improve the etch selectivity of the dielectric pedestal to the surrounding low-K inter-level dielectric for the via, to be discussed next.

The image labeled “DoD” in the figure above illustrates the wafer after dielectric-on-dielectric deposition and after removal of the SAM blocking material over the wafer, prior to the addition of the low-K dielectric.

The image on the right shows the final via connection, after low-K dielectric dep/etch and via patterning.  The added DoD material serves as a suitable “etch stop”, due to the lower etch rate compared to the low-K material.  This image illustrates the via-to-adjacent metal dielectric, in the presence of a significant overlay shift.

The figure below illustrates how the added dielectric-on-dielectric layer improves via robustness.  The “control” transmission electron microscopy image (without the DoD) shows excessive via etch of the original dielectric, with little isolation to the adjacent Mx line – not particularly tolerant of overlay error.  The DoD TEM image shows vastly improved isolation.

Experimental Electrical and Reliability Data for the SAV Process

The various figures below show the experimental data from the TSMC SAV process development team.  The Control data reflects the standard via patterning process without the selective DoD layer deposition.

  • via resistance

Both single via and via chain (yield assessment) resistance values show no difference between the control and DoD processes.

  • via-to-adjacent Mx reliability (leakage current, Vbd, TDDB)

To assess the process window, the TSMC team evaluated the leakage current and Vbd with an intentional via-to-Mx overlay shift.  Note that the control process would not support a 4nm overlay tolerance.

To ensure the additional DoD process steps did not adversely impact the characteristics of the existing Mx metal, TSMC shared evaluation data of metal lines with and without the DoD process.  The graphs below show there was no impact to metal line resistance or TDDB/electromigration reliability.

Summary

Continued interconnect scaling below the 3nm node will necessitate unique process development research to maintain electrical and reliability specs in the presence of (up to 4nm) overlay error.  The need for low-K interlevel dielectrics is a given – yet, the via etch in these materials is not especially tolerant of EPE.

TSMC has demonstrated a potential process flow for a “self-aligned via” with an additional DoD material.  The etch rate differential of the DoD results in more robust via-to-adjacent metal reliability.  This process flow utilizes two unique steps – the SAM of a blocking material on metal surfaces, and the selective ALD of a dielectric-on-dielectric.

Hopefully, selective ALD flows will transition soon from R&D to production fabrication – the potential impact of this chemistry for advanced node scaling is great.

-chipguy

References

[1]   Chen, H.-P., et al, “Fully Self-Aligned via Integration for Interconnect Scaling Beyond 3nm Node”, IEDM 2021, paper 22-1.

Note:  All images are copyright of the IEEE.

 


Technology Design Co-Optimization for STT-MRAM

Technology Design Co-Optimization for STT-MRAM
by Tom Dillinger on 01-04-2022 at 6:00 am

sense amplifier

Previous SemiWiki articles have described the evolution of embedded non-volatile memory (eNVM) IP from (charge-based) eFlash technology to alternative (resistive) bitcell devices.  (link, link)

The applications for eNVM are vast, and growing.  For example, microcontrollers (MCUs) integrate non-volatile memory for a variety of code and data storage tasks, from automotive control to financial bankcard security to IoT/wearable sensor data processing.  The key characteristics of eNVM are:

  • performance (read access time, write-verify cycle time)
  • data retention, over voltage and (especially) temperature extremes
    • bitcell “drift” over time (e.g., changes in device resistance leading to increasing bit-error rate)
  • write endurance (# of write cycles)
  • reliability (e.g., susceptibility to bit storage fails from external radiation or magnetic fields)
  • sensitivity to process variability
  • cost (e.g., # of additional mask lithography steps, compatibility of the embedded memory fabrication with existing FEOL and BEOL process steps)

(Note that the number of extra masks for embedded flash is large, and requires exposure to high programming voltage.)

  • yield (assume a double-error correction data width encoding will be used)

STT-MRAM

One of the leading eNVM technologies is the magnetic tunnel junction (MTJ) device, which uses a spin-torque transfer write current mechanism to toggle the MTJ between “parallel” (P) and “anti-parallel” (AP) states.  During a read cycle, the resistance differences between these states is sensed.

The figure below illustrates the process integration of STT-MRAM into a BEOL process for an advanced logic node. [1]

This STT-MRAM process offers a considerable cost advantage over scaling existing eFlash device technology.

In the image on the right above, the word lines run through the array connected to access devices.  During a read cycle, the column select line is grounded, and the resistance of the active MTJ determines the bitline current.  For a write cycle, since the MTJ programming current flows in opposite directions for a write to the AP state versus a write to the P state, the roles of the bitlines and column select lines are reversed, depending on the data value – i.e., write_1:  BL = 0V, CS = VPP;  write_0: BL = VPP, CS = 0V.

STT-MRAM technology does present some challenges, however.

  • small read sensing window

The read cycle needs to sense the difference in MTJ resistance between parallel and anti-parallel states.  Process variation in MTJ characteristics results in narrowing of this resistance contrast.  Sophisticated sense amplifier design methods are needed to compensate for a tight resistance margin.

  • strong MTJ sensitivity to temperature

The embedded MTJ IP will be subjected to temperature extremes both during assembly and during its operational lifetime.  The solder ball reflow and package-to-PCB attach process temperature is far higher than the maximum operational temperature, albeit only once and for a relatively short duration.  (Solder reflow temperatures are ~245C-260C.)  The operational environment for the demanding nature of MCU applications typically spans -40C to 125C.  The composition and diameter of the MTJ materials – i.e., the fixed and free magnetic layers, the tunneling oxide – are selected to maintain the spin-transfer torque properties throughout both assembly and operating temperature cycles.

Yet, due to the MTJ sensitivity to temperature, any attempt to pre-program data into the embedded STT-MRAM array prior to exposure to the assembly process temperatures would be fruitless.  Special technology-design co-optimization (TDCO) methods are needed to initialize (a portion of) the STT-MRAM array with key data measured at wafer test – more on these methods shortly.

Also, the read sensitivity – i.e., the resistance difference of P and AP states – is reduced at high temperature.  At cold temperature, the write current required to set the state of the bitcell is increased.  Again, TDCO techniques are required to compensate for these reduced margins at different temperature extremes.

  • process variation in MTJ characteristics

Sensing of the resistance differential also needs to address the process variation in MTJ devices, and the range of P and AP resistance states.

At the recent International Electron Devices Meeting (IEDM) conference in San Francisco, TSMC presented their TDCO approaches to address the STT-MRAM challenges above. [2] The rest of this article summarizes the highlights of their presentation, leading to the production release of STT-MRAM IP in their N22 ultra-low leakage process (N22ULL) node.

TSMC TDCO for N22ULL STT-MRAM

  • read sensing

When an address word line is raised along a set of bitcells in the MRAM array, current flows through the MTJ from the (pre-charged) bitline to the (grounded) select line.  The magnitude of the current on the bitline depends upon the P or AP state of the individual bitcell, and needs to be accurately sensed.  The MTJ process variation across the array suggests that each bitline sense circuit must be individually “trimmed” to match the specific local characteristics of the devices.  And, the strong temperature dependence of the MTJ needs to be dynamically compensated.

The optimized TSMC solution to MRAM bitline read sensing is illustrated below.

The read sense circuitry shown above is differential in nature, intended to amplify the voltage difference on lines Q and QB that evolves during the read cycle.  Prior to the start of the read, both nodes Q and QB are pre-charged.  When the address word line is raised, bitline current flows through the MTJ – in the figure above that is represented by current source Icell.

Note that the bitcells in the memory array are “single-ended” – i.e., there is only one connection to the sense amplifier.  (This is in contrast to a conventional 6T SRAM bitcell, for example, which provides connections to both Q and QB of the sense amplifier.)  As a result of the single connection, it is necessary to provide the QB line with a reference current, which needs to be between the Icell_P and Icell_AP values which may be flowing in the opposite side of the sense amplifier.  Further, this reference current needs to adapt to the local die temperature.

TSMC developed a unique design approach to provide the Iref value to a set of N bitcells + sense amplifiers on a word line in the array.

The figure above depicts N/2 reference MTJs that have been initialized to a P resistive state and N/2 reference MTJs in an AP state.  Their outputs have been dotted to provide a “merged” reference current.  The WL_REF signal is raised in a balanced timeframe as the active wordline – the resulting merged reference current is connected to the N sense amplifiers.  As a result, the Iref current to an individual SA is:

  ((N/2) * I_P) + ((N/2) * I_AP) / N = (I_P + I_AP) / 2

or the ideal “midpoint” current on the QB line.  After an appropriate duration into the read cycle, when a Q and QB voltage difference has been established, the Latch enable signal is raised to amplify the differential and drive Dout to the read value.

The approach to generate Iref for the sense amplifiers in an MRAM array bank provides both temperature compensation and some degree of “averaging” over process variation.

  • sense amplifier trimming

Nevertheless, MTJ process variation necessitates a per-sense amplifier correct design technique.  In the sense amplifier circuit figure above, devices N1A through N1X are in parallel with the sense pulldown transistor, all connected to Vclamp.  The switches in series with these devices represent the capability to trim the resistance of the Q line during a read cycle.  (The N2A through N2X devices provide a comparable, symmetric capability on the QB line, matching the loading on the Q line.)  During wafer-level testing, the memory BIST macro IP includes programming support to adjust the “trim code” to realize the lowest number of bit read failures during BIST, with error-correction circuitry disabled.  (This testing is performed at elevated temperature.)

  • OTP-MRAM

It was mentioned earlier that the elevated temperatures to which the MTJ is subjected during assembly preclude any attempt to write data into the array during die test.  Yet, the trim code values for each sense amplifier derived during memory BIST need to be retained in the array.  (Also, any built-in array self-repair BISR codes identified after BIST testing need to be stored.)

To address this issue, TSMC developed a unique approach, where some of the MTJ cells are subjected to a one-time programming (OTP) write sequence.  These cells retain their OTP values after exposure to the solder-reflow assembly temperature.

For these storage locations, a (tunnel oxide) “breakdown” voltage is applied to the MTJ to represent a stored ‘0’ value; the cell current will be high.  As illustrated above, any OTP junction that does not receive an applied breakdown voltage during programming will remain (P or AP) resistive, and thus will be sensed as storing a fixed ‘1’ value.

  • temperature-compensated write cycle

Whereas the sense amplifier (Rp versus Rap) read margin is reduced at high temperature, the MTJ write cycle is a greater challenge at low temps, where higher current are required to alter the MTJ state.  TSMC developed an operational write-verify cycle, where the applied write voltage is dynamically adapted to temperature.  The figure below shows a shmoo plot indicating the (wordline and bitline) write voltage sensitivity versus temperature (for AP-to-P and P-to-AP), and thus the need for compensation.

TSMC noted the “wakeup time” of the analog circuitry used to generate the corresponding write voltages adds minimally to the write cycle time.

Summary

At advanced process nodes, STT-MRAM IP offers an attractive evolution from eFlash for non-volatile storage – e.g., high retention, high durability, low additional process cost.  TSMC recently presented their TDCO approach toward addressing the challenges of this technology, adopting several unique features:

  • improved read sensing between Rp and Rap
    • derivation of read sense amplifier reference current compensated for temperature, with process variation averaging
    • per sense amplifier “trimming” for optimal read bit error rate
  • one-time programming cell storage prior to solder reflow assembly, to retain trim codes and array repair values
  • a temperature-compensated write voltage applied to the MTJ (as part of the write-verify cycle)

The characteristics and specs for the TSMC N22ULL STT-MRAM IP are appended below.

To quote TSMC, “Each emerging memory technology has its own unique advantages and challenges.  Design innovation is essential to overcome the new challenges and bring the memory IP to market.”

-chipguy

References

[1] Shih, Yi-Chun, et al., “A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process”, IEDM 20, paper 11.4.

[2] Chih, Yu-Der, et al., “Design Challenges and Solutions of Emerging Nonvolatile Memory for Embedded Applications”, IEDM 2021, paper 2.4.

Note:  All images are copyright of the IEEE.

 


Advanced 2.5D/3D Packaging Roadmap

Advanced 2.5D/3D Packaging Roadmap
by Tom Dillinger on 01-03-2022 at 6:00 am

SoIC futures

Frequent SemiWiki readers are no doubt familiar with the advances in packaging technology introduced over the past decade.  At the recent International Electron Devices Meeting (IEDM) in San Francisco, TSMC gave an insightful presentation sharing their vision for packaging roadmap goals and challenges, to address the growing demand for greater die integration, improved performance, and higher interconnect bandwidth.[1]  This article summarizes the highlights of the presentation.

Background

2.5D packaging

2.5D packages enable multiple die to be laterally positioned in close proximity, with signal redistribution interconnect layers (RDL) between the die fabricated on a silicon interposer present between the die and package substrate.  Through silicon vias (TSVs) provide the connectivity to the substrate.

The TSMC implementation of this technology is denoted as Chip-on-Wafer-on-Substrate (CoWoS), as was introduced a decade ago using multiple FPGA die in the package to expand the effective gate count.

The emergence of high bandwidth memory (HBM) stacked die as a constituent of the 2.5D integration offered system architects with new alternatives for the memory hierarchy and processor-to-memory bandwidth.

The development investment in 2.5D technology grew, now enabling the silicon interposer area to greatly exceed the “1X maximum” reticle size, to accommodate more (and more diverse) processing, memory and I/O die components (aka, “chiplets”).

Additional package fabrication steps incorporate local “trench capacitors” into the interposer.  Oxide-poly-oxide-poly material layers fill the trench, with the poly connected to the RDL supply metal.  The resulting decoupling capacitance reduces power supply droop considerably.

Alternative technologies have also been developed, replacing the full area silicon interposer with a local “silicon bridge” (CoWoS-L) between adjacent die embedded in an organic interposer, thus reducing cost (albeit with relaxed RDL interconnect dimensions).

Concurrently, for very low cost applications, the demand for higher I/O count die than could be supported with the conventional wafer-level chip-scale package (WLCSP) led to the development of a novel technology that expands the die surface area with a “reconstituted wafer”, on which the redistribution to a larger number of I/O bumps could be fabricated.

This Integrated FanOut (InFO) technology was originally developed for single die (as a WLCSP-like offering).  Yet, the application of this technique is readily extended to support the 2.5D integration of multiple heterogeneous die placed adjacent, prior to the reconstitution step. (The InFO_oS technology will be discussed shortly.)

3D die stacking

3D die stacking technology has also evolved rapidly.  As mentioned above, the fabrication of TSVs spanning between layers of DRAM memory die with “microbumps” attached at the other end of the TSV has enabled impressive levels of vertical stacking – e.g., eight memory die plus a base logic controller die in an HBM2e configuration.

Similarly, through-InFO vias (located outside the base die in the reconstituted wafer material) has enabled additional micro-bumped die to be vertically stacked above the base InFO die – e.g., a memory die on top of a logic die.

The most recent advancement in 3D stacking technology has been to employ bump-less “direct bonding” between two die surfaces.  Applying a unique thermal + compression process, two die surfaces are joined.  The metal pad areas on the different die expand to form an electrical connection, while the abutting dielectric surfaces on the two die are bonded.  Both face-to-face (F2F) and face-to-back (F2B) die orientations are supported.  The planarity and uniformity (warpage) requirements of the surfaces are demanding; particulates present on the surface are especially problematic.  TSMC denotes their 3D package technology as System-on-Integrated Chips, or “SoIC”.

As product architects are exploring the opportunities available with these packaging technologies, there is growing interest in combining “front-end” 3D stacked SoIC configurations with 2.5D “back-end” (InFO or CoWoS) RDL patterning and assembly.  The collective brand that TSMC has given to their entire suite of advanced packaging offerings is “3D Fabric”, as illustrated below.

TSMC 3D Fabric Roadmap

At IEDM, TSMC shared their strategy for improving performance, power efficiency, signal bandwidth, and heat dissipation for these technologies.  (The majority of the focus was on bonding technology for SoIC.)

CoWoS (2.5D)

    • increase package dimensions to 3X maximum reticle size for the Si interposer
    • expectation is that stacked SoIC die will be integrated with multiple HBM stacks

InFO_oS (2.5D)

The original InFO offering was as an evolution to WLCSP, first as a single die, and then as a base die with another added on top connected to the through-InFO vias.  TSMC is also expanding the InFO offering to support multiple adjacent die embedded in the reconstituted wafer; the RDL layers are then fabricated and microbumps added for attach to a substrate (InFO-on-Substrate, of InFO_oS).  A projection for the InFO_oS configurations to be supported is illustrated below.

SoIC (3D)

The roadmap for 3D package development is shown below, followed by a table illustrating the key technical focus – i.e., scaling the bond pitch of the (F2F or F2B) stacked connections.

The bond pitch (and other metrics) for microbump technology evolution are included with the SoIC direct bonding measures in the table above for comparison.

As shown in the table above, TSMC has defined a new (relative comparison) metric to represent the roadmap for 3D stack bonding technology – an “Energy Efficiency Performance” (EEP) calculation.  Note that the target gains in EEP are driven by the aggressive targets for scaling of the bond pitch.

EEP = (bond_density) * (performance) * (energy efficiency)

Much like the IC scaling associated with Moore’s Law, there are tradeoffs in 3D bond scaling for performance versus interconnect density.  And, like Moore’s Law, the TSMC roadmap goals are striving for a 2X improvement in EEP for each generation.

SoIC Futures

As an illustration of the future potential for 3D stacking, TSMC provided an example of a three-high stacked structure, as shown below.

Note that the assumption is that future HBM stacks will migrate from a microbump attach technology within the stack to a bonded connection – the benefits of this transition on performance, power, and thermal resistance (TR) are also shown in the figure.

heat dissipation

Speaking of thermal resistance, TSMC emphasized the importance of both the bonding process for low TR and design analysis of the proposed 3D stack configuration, to ensure the junction temperature (Tj) across all die remains within limits.

The IEDM presentation referred to additional research underway at TSMC to evaluate liquid-cooling technology options. [2] As illustrated below, “micro-pillars” can be etched into a silicon lid bonded to the assembly, or even directly into the die, for water cooling.

Summary

Advanced 2.5D and 3D packaging technologies will provide unique opportunities for systems designers to optimize performance, power, form factor (area and volume), thermal dissipation, and cost.  TSMC shared their development roadmap for both 2.5D and 3D configurations.

The 2.5D focus will remain on support of larger substrate sizes for more (heterogeneous) die integration;  for markets focus on cost versus performance, different interposer/bridge (CoWoS) and reconstituted wafer (InFO technology options are available.

3D stacking technology will receive the greatest development focus, with an emphasis on scaling the interface bond pitch.  The resulting “2X improvement in EEP” for each SoIC generation is the target for the new “More than Moore” semiconductor roadmap.

-chipguy

References

[1] Yu, Douglas C.H., et al, “Foundry Perspectives on 2.5D/3D Integration and Roadmap”, IEDM 2021, paper 3-7.

[2]  Hung, Jeng-Nan, et al., “Advanced System Integration for High Performance Computing with Liquid Cooling”, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), p. 105-111.

Note:  All images are copyright of the IEEE.


US Supply Chain Data Request Elicits a Range of Responses, from Tight-Lipped to Uptight

US Supply Chain Data Request Elicits a Range of Responses, from Tight-Lipped to Uptight
by Craig Addison on 11-14-2021 at 6:00 am

China TSMC Supply chain woes 2021
Chinese state-run media blames Taipei for allowing Taiwan Semiconductor Manufacturing Co to submit chip supply information to the US government. Photo: Shutterstock

TSMC drew the ire of Chinese state media last week after it complied with the US Department of Commerce request to submit supply chain data by the November 8 deadline.

The Chinese reports, which called it an act of “surrender” to US hegemony, were careful in laying blame on Taipei for caving in to Washington, rather than pointing fingers at TSMC itself.

Chinese state media commentators are experts in party propaganda, not semiconductors, so they could be excused for not knowing the obvious: TSMC didn’t become the world’s leading foundry by blabbing about what its customers are doing.

Separately, Reuters quoted TSMC saying that it did not disclose any detailed confidential customer information to the US.

TSMC was one of 23 entities, including ASE, Infineon, Micron and Philips, that provided supply chain data, with most chipmakers choosing to do so privately rather than publicly disclosing their data.

But there were some interesting nuggets to be found in the public submissions.

On the customer side, Philips revealed that it had to delay 13 per cent of its production due to the semiconductor shortage. It added that the most severe shortages were in MCUs, FPGAs, ASICs, memory, linear and discretes – and that sourcing hard-to-find components now takes 12 to 18 months compared to 3 months in normal times.

Technicolor was something you’d see on movie screens in the golden days of Hollywood. These days it is the trading name of a French based company (formerly Thomson) that provides, among other things, visual effects production services for movies. It also buys chips, but not anywhere near the quantity of a giant like Philips – and therein lies the problem.

As a small customer, Technicolor has little clout amid product shortages, and it expressed those frustrations in its submission.

“Technicolor’s IC supply chain visibility has been challenged and remains uncertain, with unstable raw material supply (lead-frame, substrate), shortages with IC fabs and OSAT balancing capacity (allocation) and material availability to prioritize supply impacting delivery schedules with the fluctuation in lead-time impacting delivery commitments,” the company said.

Rising costs from foundry suppliers like TSMC and UMC was another bone of contention for the French company.

“IC suppliers are requesting customers to pay expediting fees to secure supply from foundries, and logistic fees are ever rising from our freight forwarders.  Cost increases like this are not standard in the semiconductor market and go against Moore’s Law, which is why they were not foreseeable or expected.” Ouch!

Back on the chip supply side, Infineon was blunt in telling the US government what the “root cause” for the global chip shortage was: the JIT (just-in-time) manufacturing system.

“To really overcome the global chip shortage, the JIT system should be replaced by a collaborative platform where demand information is shared anonymously (to keep the competition going) but without the bullwhip bias,” Infineon said.

The bullwhip effect refers to the demand distortion that travels upstream in the supply chain, amplified by the lack of synchronization among supply chain members.

The most damning submission, though, came from the Institute for New Economic Thinking, which slammed member companies of the Semiconductor Industry Association (SIA) like Intel and Qualcomm for asking the US government for industry funding on the one hand, but using their spare cash for stock buybacks on the other. The latter, of course, is meant to boost share prices and increase the wealth of stock-holding executives at the companies.

“Most of the SIA corporate members now lobbying for the CHIPS for America Act have squandered past support that the US semiconductor industry has received from the US government for decades by using their corporate cash to do buybacks to boost their own companies’ stock prices,” report authors William Lazonick and Matt Hopkins charged.

“Among the SIA corporate signatories of the letter to President Biden, the five largest stock repurchasers – Intel, IBM, Qualcomm, Texas Instruments, and Broadcom – did a combined $249 billion in buybacks over the decade 2011-2020, equal to 71 percent of their profits and almost five times the subsidies over the next decade for which the SIA is lobbying.”

It’s not only chipmakers that do this. The Semiconductors in America Coalition (SIAC) was formed in May to lobby Congress for the passage of the CHIPS act. Members include Apple, Microsoft, Cisco and Google, who spent a combined $633 billion on buybacks during 2011-2020, according to the report, which pointed out this was about 12 times the proposed government subsidies under CHIPS to support wafer fabs on US soil.

“If the Congress wants to achieve the legislation’s stated purpose of promoting major new investments in semiconductors, it needs to deal with this paradox,” the report authors said.

Their suggestion: require the SIA and SIAC to extract pledges from members to end stock buybacks as open-market repurchases over the next 10 years.

Any bets on how the members will vote on that?

The Chip Warriors podcast series


Taiwan Semiconductor Outlook May 1988

Taiwan Semiconductor Outlook May 1988
by Daniel Nenni on 11-12-2021 at 6:00 am

James E. Dykes

This is an interesting piece of TSMC history. From 1987 to 1988 James E. Dykes served as the first President and Chief Executive Officer of Taiwan Semiconductor Manufacturing Company Ltd.

Taiwan Semiconductor Outlook
by James E. Dykes
President & Chief Executive Officer
Taiwan Semiconductor Manufacturing Company

Given at:

Fourth Annual In-Stat Inc. Semiconductor Forum

Held at the Pointe at South Mountain.
Phoenix, Arizona
Monday, May 2, 1988

— Opening Comments —

As Jack said, I’m here to talk about the Taiwan semiconductor outlook.

That outlook is, in a word, great.

The Economist Magazine, in its March 5 issue, called Taiwan and its nearly 20 million people “The most dynamic country in east Asia.” And it’s all true. The country is going through a rare and rapid period of enlightenment.

Politically, martial law has been lifted, newspaper censorship and control have been revised, and new political reforms are expected to continue under President Lee Teng-hui, who took office in January after the death of President Chiang Ching-kuo.

Economically, productivity is rising at a record rate. In 1952, for example, per capita GNP was $48. Today it’s more than $5,000 and next year, it’s projected to be more than $6,000. In response to U.S. trade pressures, import tariffs across a whole range of goods are being sharply reduced. And Taiwan’s foreign exchange reserves exceed $75 billion, the world’s third largest after Japan and west Germany. All this in a country with few natural resources.

Yet to really understand the impact Taiwan will have on the semiconductor industry, you have to know why the country is in transition. For a variety of reasons, Taiwanese manufacturers are heading upmarket across a whole range of industries and leaving behind their image as manufacturers of cheap, shoddy, or imitation goods.

Korea and Taiwan are often mentioned as exhibiting the same trends, but the driving forces are quite different. Korea is dominated by large, vertically integrated companies, the chaebol, with massive government investment and direction for strategic industries.

Taiwan, by comparison, is more like Silicon Valley. You find in Taiwan the same entrepreneurial spirit the same willingness to trade hard work for business success and the opportunities to make it happen, that you find in Santa Clara County, and here in the Valley of the Sun. Even Taiwan’s version of Wall Street will seem familiar to many of you. There’s a red-hot stock market where an entrepreneur can take a company public and become rich overnight.

The Taiwanese people are hard-working and well-educated. One in every four is a student and the literacy rate is 91%. Society as a whole is stable and is becoming more affluent, the average family income last year of over $18,000 is projected to rise to more than $40,000 in the early 1990s. Yet the nation’s wealth is distributed fairly equitably, with the wealthiest 20% of households having an income less than five times that of the poorest 20%.

The society is becoming more cosmopolitan. Three-quarters of the population now live in urban areas and agriculture as a percentage of gross domestic product has dropped from about one-third in 1952 to about than one-twentieth today.

During the same time period, the percentage of industrial output more than doubled and now accounts for about half of GDP.

Taiwan, as a whole, has a GNP of about $98 billion, but the more telling economic statistics have to do with the volume and type of foreign trade. Because the country’s economic growth has been fueled largely by exports and Taiwan now faces a different set of export conditions.

In 1953, Taiwan’s overall foreign trade amounted to $320 million. In 1986, total foreign trade amounted to about $64 billion, and the country ran a $16.6 billion surplus with the U.S., its largest trading partner.

Overall, Taiwan’s trade surplus was about $19 billion.

As I said earlier, Taiwan has foreign exchange reserves of more than $75 billion. But it has a foreign debt of only about $3 billion. And as you know, Taiwan’s rising trade surplus has brought U.S. protests. including a decision by the U.S. administration to remove Taiwan from the generalized system of preferences program, which exempts selected countries and product categories from U.S. import tariffs.

In response to the overall trade situation, Taiwan has acted in a number of areas, reducing its own import tariffs on a range of products, widening its market to foreign goods and services and spending more on capital-intensive domestic public-works projects. Even boating and coastal fishing are being opened and targeted as tourist attractions.

Currency exchange rates are also changing the nature of many Taiwanese enterprises. Over the last few years, the Taiwan dollar has appreciated dramatically against the U.S. dollar, nearly 20% in 1987 alone. Clearly, Taiwan is losing its edge as a source of low-cost labor.

The government is actively encouraging Taiwanese companies to look for more domestic markets, to find export opportunities in countries other than the U.S., to move upmarket, to products of greater sophistication with greater added-value and competitive worth and to increase R&D expenses.

The electronics industry accounted for 4.2% of Taiwan’s GNP last year and 20% of the value of exports. Planners talk about raising the proportion of such technology-intensive industries from the current 24% to 35% of the manufacturing sector by next year.

You can look at semiconductors as a microcosm of this overall trend.

While the Taiwanese have historically served the labor-intensive test and assembly segments, they are moving upmarket into silicon integrated circuit production. The value of ICs shipped from 1979 to 1985 grew by almost 195%, from $133 million to $391 million.

The value of transistor shipments grew by an impressive but smaller 111%, while growth in the value of low-technology diodes and capacitors remained virtually flat in the same time period.

The emphasis is obviously changing. As you know, semiconductor consumption is a barometer of end-use electronics production. According to Dataquest, last year total Taiwan semiconductor consumption was about $1.1 billion out of a worldwide $37 billion. This year, Taiwan’s semiconductor consumption is projected to rise by 31.5%, versus 20% worldwide. In dollar terms, Taiwan’s share is expected to grow to more than $3 billion over the next five years for a compound annual growth rate of 22.5%.

The major chip end-users in Taiwan are manufacturers of personal computers and associated products and consumer electronics equipment chiefly VCRs and TVs. Broken down by segment, the personal computer area will show 22.3% compound annual growth in the next five years, followed by the VCR segment at 11%, and TV production at about 8.5%.

Two trends here underscore the move upmarket from test and assembly activities: one, the Japanese are moving production of high-performance consumer electronics to Taiwan, and two, the government is encouraging Taiwanese companies to develop their own manufacturing skills in products with high growth potential: CDs, digital TV, digital audio tape.

The semiconductor industry in Taiwan is beginning to blossom. It’s interesting to note that although Taiwan’s growth as a semiconductor supplier was fueled largely by foreign firms until the early 1980s. The island’s first semiconductor factory for transistors was started in 1963 by a native Chinese with technology developed at Cheng Kung University.

Following that, of course, there was a virtual explosion of discretes production, beginning with general instrument, which established a facility for germanium transistors in 1965. That was soon followed by investments in assembly facilities by Texas Instruments and American Microsystems, and later by a host of others.

By 1984, there were 57 companies and organizations in semiconductors, 13 of them in ICs, and 44 in discretes and optoelectronics.

The Hsinchu Science Park, where we are based, is home to an increasing critical mass of semiconductor companies alongside other firms engaged in electronics design and production, there are about 70 high-technology companies located there today. The concept is to have semiconductor producers and customers in the same industrial complex.

Let me describe the IC-related firms in Taiwan. Besides ERSO, the governmental electronic research service organization, there are eight firms with wafer and/or IC manufacturing capability. They are TSMC, United Microelectronics Corporation, or UMC, Vitelic, Mosel, Quasel, Hualon, Winbond, and UTIC.

Taiwan has a combined capability to produce 61,000 4-inch wafers per month now.

But with already announced expansion plans, by 1990 Taiwanese producers will have the additional monthly capability for 80,000 6-inch wafers and 35,000 5-inch wafers.

There are more than 40 new design houses, like STK, Holtek, and Silicon Integrated Systems. ERSO serves as a photomask supplier and a new mask shop is now being incorporated. It’s called Taiwan Mask Corporation and it will consist of the ERSO facilities now being used plus new investment in the science park for additional e-beam mask-making capability.

And of course, there are more than 30 assembly and test facilities on the island, TI, Philips, General Instrument, GE Solid State, and so on.

Dataquest ranked UMC third in 1987 as a supplier of MOS logic devices in the Asia-Pacific/rest of world market. In 1987, ERSO and UMC accounted for nearly 3% of total semiconductor production in that market 7% of total MOS production and 10% of total MOS logic devices.

Taiwan’s future IC design efforts will likely focus on ASIC circuits and CAD tools. Process options will include sub-micron CMOS, and several others: BiCMOS, CCDs, power ICs, thin-film devices, and gallium arsenide. Package development will be directed at high pin-count and multi-chip, multi-layer configurations.

However, much work remains to be done for this to happen. If Taiwan is to achieve its IC goals in the next five years, it must develop an infrastructure adequate to serve local industry needs. The most pressing need is for a locally based network of material, equipment and service suppliers to support the growth of the industry.

Let me give you a sense of that projected growth. Winbond is a maker of ICs for the personal computer, telecommunications, and consumer electronics industries. It now has sales of less than $35 million but plans to be a $100 million company by 1991 with 300 employees instead of its current 110.

It is building a class 10 wafer fab in the Science Park, with a capacity of 15,000 5-inch wafers per month. The fab will run 2-micron CMOS and NMOS processes and will be ready in September. A second fab is under serious consideration for operation in 1992.

UMC is building a new 6-inch fab to add capacity of 30,000 6-inch wafers per month. The company expects to spend about $140 million over the next three years for capacity additions.

TSMC is building a new manufacturing facility in the Science Park, with a capacity for 30,000 6-inch CMOS wafers per month, although a portion is convertible to 8-inch. The entire facility is designed for sub-micron geometries, but initial production will center on 1.2-micron feature sizes. It is geared toward turnkey production, from reticle generation to assembly and final test… And we expect it to be operational by the end of next year.

And design house SiS projects a 240% increase in sales to $68 million in 1992.

As you can see, Taiwan is growing and maturing. It is becoming a more respected competitor in the world’s economy and is leaving behind its heritage of disrespect for intellectual property rights.

There are risks and rewards for technology companies who wish to ally themselves with the most dynamic country in east Asia. The risks generally have to do with issues of technology development and availability.

The rewards generally have to do with what you might expect from dealing with a proud, talented, and hard-working people. Quality products at competitive prices and long-term, mutually beneficial relationships.

Thank you very much.


Update on TSMC’s 3D Fabric Technology

Update on TSMC’s 3D Fabric Technology
by Tom Dillinger on 11-03-2021 at 8:00 am

3D eTV testchip

TSMC recently held their 10th annual Open Innovation Platform (OIP) Ecosystem Forum.  An earlier article summarized the highlights of the keynote presentation from L.C. Lu, TSMC Fellow and Vice-President, Design and Technology Platform, entitled “TSMC and Its Ecosystem for Innovation” (link).

Overview of 3D Fabric

The TSMC 3D Fabric advanced packaging technology spans both the 2.5D and vertical die stacking offerings, as depicted below.

The Integrated FanOut (InFO) packages utilize a reconstituted wafer consisting of die embedded face down, surrounded by a molding compound (link).

Redistribution interconnect layers (RDL) are fabricated on the epoxy wafer.  (InFO-L refers to a silicon “bridge chiplet” between die embedded in the InFO package for improved inter-die connectivity over the RDL metallization pitch.)

The 2.5D CoWoS technology integrates die (and often, high-bandwidth memory stacks) on an interposer utilizing microbump attach.  The original CoWoS technology offering (now CoWoS-S) used a silicon interposer, and related silicon-based lithography for RDL fabrication;  through-silicon vias (TSVs) provide connectivity to the package bumps.  The silicon interposer technology offers improved interconnect density, critical for the high signal count HBM interface.  More recently, TSMC has been offering an organic interposer (CoWoS-R), providing a tradeoff between interconnect density versus cost.

The 3D SoIC offering provides vertical integration utilizing hybrid bonding between die pads.  The die may be oriented in face-to-face or face-to-back configurations.  TSVs provide connectivity through the (thinned) die.

InFO and CoWoS offerings have been in high-volume production for several years.  The recent innovations in CoWoS development relate to expanding the maximum silicon interposer dimensions to greater than the maximum reticle size to accommodate a larger number of die (especially, HBM stacks), stitching together the RDL interconnects.

The majority of Jim’s presentation covered advanced in SoIC development.

SoIC Testchip

TSMC shared results of a recent SoIC qualification test vehicle, as shown below.

The configuration used was the vertical bonding of an (N5) CPU die with an (N6) SRAM die, in a face-to-back topology.  (Indeed, a major CPU vendor has pre-announced plans for a vertical “last-level” SRAM cache die attached to a CPU using TSMC’s SoIC, to be available in 1Q2022.)

SoIC Design Flow

Jim presented a high-level design flow for vertical die integration, as shown in the figure below.

The flow requires concurrent focus on both top-down system partitioning into individual die implementations, plus early analysis of the thermal heat dissipation in the composite configuration, as highlighted above.

The discussion on thermal analysis highlighted the “chimney” nature of the low thermal resistance paths of the BEOL PDN and interconnect, compared to the surrounding dielectrics, as shown above.  Specifically, TSMC has collaborated with EDA vendors on improving the accuracy of the SoIC model discretization techniques, applying a more detailed mesh in specific “hotspot” areas initially identified with a coarse grid analysis.

TSMC also presented a methodology recommendation to incorporate thermal analysis results into the calculation of SoIC static timing analysis derate factors.  Much like on-chip variation (OCV) is dependent upon the distance spanned by (clock and data) timing paths, the thermal gradient for the SoIC paths is an additional derate factor.  TSMC reported that on-die temperature gradients for a path are typically ~5-10C, and a small flat derate timing margin for temperature should suffice.  For SoIC paths, large gradients of ~20-30C are feasible.  A flat derate to cover this range would be too pessimistic for paths with a small temperature difference – results of SoIC thermal analysis should be used for derate factor calculation.

SoIC Testing

The IEEE 1838 standardization effort pertains to the definition of die-to-die interface testing (link).

Much like the IEEE 1149 standard for boundary-scan chains on-die for package-to-package testing on a printed circuit board, this standard defines the control and data signal ports on each die for post-stack testing.  The primary focus of the standard is to exercise the validity of the face-to-face bonds and TSVs introduced during SoIC assembly.

Jim indicated that this definition is sufficient for low-speed I/Os between SoIC die, yet a more extensive BIST method will be required for high-speed I/O interfaces.

TSMC Foundation IP for SoIC – LiteIO

TSMC’s library development teams commonly provide general-purpose I/O cells (GPIOs) for each silicon process node.  For the die-to-die connections in SoIC configurations, where the driver loading is less, TSMC offers a “LiteIO” design.  As illustrated below, the LiteIO design focuses on optimizing the layout to reduce parasitic ESD and antenna capacitances, to enable faster datarates between die.

EDA Enablement

The figure below lists the key tool features recently developed in collaboration with major EDA vendors for the InFO and SoIC package technologies.

Summary

TSMC continues to invest heavily in 2.5D/3D advanced packaging technology development.  The key recent initiatives have focused on the methodology for 3D SoIC direct die attach – i.e., partitioning, physical design, analysis.  Specifically, early thermal analysis is a mandatory step.  Additionally, TSMC shared results of their SoIC eTV qualification testchip vehicle.  2022 is shaping up to see the rapid emergence of 3D SoIC designs.

-chipguy

Also read:

Highlights of the TSMC Open Innovation Platform Ecosystem Forum

Highlights of the TSMC Open Innovation Platform Ecosystem Forum

 

 


On-Chip Sensors Discussed at TSMC OIP

On-Chip Sensors Discussed at TSMC OIP
by Tom Simon on 11-02-2021 at 10:00 am

phase noise correlation

TSMC recently held their Open Innovation Platform (OIP) Ecosystem Forum event where many of their key partners presented on their latest projects and developments. This year one of their top IP provider partners, Analog Bits, gave two presentations. Analog building blocks have always been necessary as enabling technology on leading edge designs. The move to 3nm continues this important relationship. Analog Bits has developed specialized analog IP that can help differentiate end products. For instance, they have focused on optimized high performance and low power SerDes, among other things. Another significant area is specialized on-chip sensors for monitoring chip health and performance.

In his presentation Mahesh Tirupattur, Analog Bits’ EVP, discussed how their sensing IP was used by Cerebras in developing the largest chip ever designed. The Cerebras WSE-2 has 2.6 trillion transistors in 850,000 optimized cores covering 46,225 square mm of silicon.  Cerebras faced challenges in power distribution and power supply integrity. Analog Bits IP offered them a solution to monitor chip operation in real time that can be used to apply real time corrective actions. They used 840 distributed glitch detectors to provide real time coverage of the entire design. The Analog Bits glitch detectors can detect short duration events that could otherwise easily be missed. They are programmable for trigger voltage, depth of glitch and time span of glitch. Their sensitivity exceeds 5pVs.

Recently Analog Bits expanded their sensor offering by adding power supply glitch detectors with an integrated voltage reference to their lineup of integrated POR sensors and on-die PVT sensors. This allows them to cover all aspects of chip operation in real time, including POR conditions – and now the health of the power supplies.

Of course, sensors require extremely high accuracy to correctly report chip behavior. Similarly, clocking macros need accuracy to enable proper chip operation. So, it was good to see that their second presentation at OIP was specifically on the topic of design and verification of these blocks. The paper was titled “Design and Verification of Clocking Macros and Sensors in N5 and N3 Processes Targeting High Performance Compute, Automotive, and IoT Applications”, and authored by Sweta Gupta, Director of Circuit Engineering at Analog Bits and Greg Curtis, Sr. Product Manager of Siemens EDA. The paper itself was the result of a three-way collaboration between TSMC, Siemens and Analog Bits.

In the second presentation Analog Bits shared correlation data on silicon measurements to specification for several of their PLLs, a power supply droop detector and a temperature sensor. Here is one of their slides on the phase noise correlation between measurement and silicon for a PLL built in TSMCs N5.

phase noise correlation

Analog Bits has a broad and well thought out portfolio of analog IP. They have customers on a wide range of processes from 0.25um to 3nm. I am sure that part of their success stems from their no-royalty business model. They have billions of units shipped from over a thousand IP deliveries since they first started in 1995. While the OIP presentations are over, more detailed information on all of their IP for on-chip sensors, SerDes, clocks and I/Os is available by contacting them. Their website offers detailed products listings & data sheets, and access to their N5 test chip video.

Also read:

Package Pin-less PLLs Benefit Overall Chip PPA

Analog Sensing Now Essential for Boosting SOC Performance

Analog Bits is Taking the Virtual Holiday Party up a Notch or Two