TSMC – Page 12 – SemiWiki

March 3, 2021March 26, 2023

Semiconductor Shortage – No Quick Fix – Years of neglect & financial hills to climb

Semiconductor Shortage – No Quick Fix – Years of neglect & financial hills to climb
by Robert Maire on 03-03-2021 at 8:00 am
Categories: China, Semiconductor Advisors, Semiconductor Services, TSMC
7 Comments

– Semi Situation Stems from long term systemic neglect
– Will require much more than money & time than thought
– Fundamental change is needed to offset the financial bias
– Auto industry is just the hint of a much larger problem

Like recognizing global warming when the water is up to your neck

The problem with the semiconductor industry has finally been recognized but only after it stopped the production of the beloved F150 Pick Up truck and Elon’s Tesla. Many analysts and news organizations wrongly blame the Covid pandemic and its many consequences and assume this is just another example of the Covid fallout. Wrong! This has been a problem decades in the making. Its not new. The fundamental reasons have been in the works for years. The only thing the pandemic did was to bring the issue to the surface more quickly.

The issue could have been brought to the surface just as easily and with worse consequences by a conflict between China and Taiwan. Or perhaps another trade spat between Japan and Korea.

The semiconductor industry is perhaps not as robust as would otherwise be thought given that it hasn’t seen a significant problem before.

The reality is that the “internationalization” of both the industry and its supply chain have opened it up to all manner of disruption coming at any point along that long chain.

The consolidation has further concentrated the points of failure into a small handful of players and perhaps one, TSMC, that is 50+% of the non memory chip market.

Tamagotchi Toys were the Canary in a Coal Mine

Most people may not remember those digital pets called Tamagotchi that were a smash hit in the late 90’s. Many in the semiconductor industry in Taiwan do remember them. In the summer of 1997 they sucked up a huge amount of semiconductor capacity in Taiwan and whacked out the entire chip industry for the entire summer causing delays and shortages of all types of chips.

Tamagotchi Tidal Wave Hits Taiwan

In essence, a craze over a kids toy created shortages of critical semiconductor chips. Semiconductor capacity is much greater now than it was 20 years ago but the industry remain vulnerable to demand spikes and slowdowns.

The memory industry is an example of the problem

Perhaps the best example of the chip industry’s vulnerability is the memory semiconductor market. The market lives on the razors edge of supply and demand and the balance maintained between the two.

Too much demand and not enough supply and prices skyrocket….too little demand and excess supply and prices collapse.

The memory industry is clearly the most cyclical and volatile in the semiconductor universe. One fab going off line for even a short while due to a power outage or similar causes the stop market for memory chips to jump.

Kim Jong-Un should buy memory chips futures

All it would take is one “accidentally” fired artillery round from North Korea that hit a Samsung fab in South Korea and took it out of commission. Memory prices would go through the roof for a very long time as the rest of the industry could never hope to make up for the shortage caused in any reasonable amount of time

Other industries, such as oil, do not have the same problem

When you look at other industries in which a product is a commodity like memory is you do not have the same production problem. The oil industry which is also a razor’s balance between supply and demand does not have the same issue as there is a huge amount of excess capacity ready to come on line at a moments notice.

The cost of oil pumps and derricks sitting around idle waiting to be turned on is very very low as compared to the commodity they pump. This means the oil industry can flex up and down as needed by demand and easily make up for the shortage if someone goes off line (like Iran).

Imagine if the oil industry kept pumping, at full output, never slowing, for each new oil field drilled.

In the semiconductor industry the capital cost is essentially the whole cost so fabs never ever go offline as the incremental cost to produce more chips is quite low. This means there is no excess capacity in the chip industry of any consequence and they run 24X7. Capacity is booked out months in advance and capacity planning is a science (perfected by TSMC).

The semiconductor industry has all the maneuverability of a super tanker that takes many miles to slow down or speed up….you just can’t change capacity that easily.

There is no real fix to the capacity issue due to financials

To build capacity that could be brought on line in a crisis or time of high demand would require an “un-natural” act. That is spending billions to build a fab, only to have it sit there unused waiting for the capacity to be needed. This scenario is not going to happen….even the government isn’t dumb enough to spend billions on a “standby” factory that needs a constant spend to keep up Moore’s law.

Its just not going to happen

Moving fabs “on shore” just reduces supply risk not demand risk

Rebuilding fabs in the US would be a good thing as it would mean fabs that are no longer an artillery shell away from a crazy northern neighbor or an hour boat ride away from a much bigger threat that still claims to own you.

That will certainly help reduce the supply side risk assuming we don’t build the new fabs on fault lines or flood zones. The demand side variability will still exist but could be managed better.

Restarting “Buggy Whip” manufacturing

The other key thing that most people do not realize is that most semiconductors used in cars, toys and even defense applications are made in very old fabs. All those older fabs that used to make 386 and 486 chips and 1 megabit memory parts have long ago been sold for scrap by the pound and shipped off to Asia (China) and are now making automotive and toaster oven chips.

Old fabs never die…they just keep making progressively lower value parts. As I have previously mentioned in a prior note, you don’t make a 25 cent microcontroller for a car in a $7B , 5NM fab….the math simply doesn’t work.
This ability to keep squeezing value out of older fabs has worked as demand for trailing edge has not exceeded capacity.

For a typical chip company, the leading edge fab makes the highest value CPU, the next generation older fab maybe makes a GPU, the next older fab maybe some I/O chips or comms chips, the older fab makes consumer chips and the oldest fabs make chips for TV remotes.

In bleeding edge fabs the equipment costs are the vast majority with labor being a rounding error. In older fabs , with fully depreciated equipment, labor starts to become a factor so many older fabs are better suited to be packed up and shipped off to a low labor cost country.

The biggest problem is that demand for older chip technology seems to have exceeded the amount of older capacity in the world as chips are now in everything and IOT doesn’t need bleeding edge.

Equipment makers for the most part don’t make 6 inch (150MM) tools anymore, some still make their old 8 inch (200MM) some don’t. As we have previously mentioned, demand for 200MM now exceeds what it was in their peak.

Old Tools are being Hoarded

Summary
Fixing not only the shortage issue but the risk issue will take not only a lot of time but a lot of money. The problem is systemic and has been dictated by financial math that has incentivized what we currently have in place.

In order to change the behavior of anyone who runs a chip company and can add we need to put in place financial incentives, legal decrees, legislative incentives and use a multiple of levers to change the current dynamics of the industry.

Even with all the written motivation in place it will still take years for the physical implementation of the incentivized changes.

TSMC has been under enormous pressure for years about a fab in the US. Now they are planning one in Arizona that is still years away, will be old technology when it comes on line and will barely be a rounding error….. all that from a multi billion dollar effort….. but its a start.

A real effort is likely to be well north of $100B and 10 to 20 years in the making before we could get back to where the US was in the semiconductor industry 20 years ago.

The Stocks
As the saying goes, buying semiconductor equipment company stocks is like buying a basket of the semiconductor industry. They can also be view as the “arms merchants” in an escalating war.

It doesn’t matter who wins or loses in the chip industry but building more chip factories is obviously good for the equipment makers, in general.

In the near term, foreign makers such as Tokyo Electron, ASM International, Nova Measuring and others may make for an interesting play.

There is plenty of time as we are sure that no matter what happens we will see zero impact from government sponsored activities in 2021 and it will likely take a very long time to trickle down so we would beware of “knee jerk” reactions that may drive the stocks near term.

Also Read:

“For Want of a Chip, the Auto Industry was Lost”

Will EUV take a Breather in 2021?

New Intel CEO Commits to Remaining an IDM

March 2, 2021March 4, 2021

Features of Resistive RAM Compute-in-Memory Macros

Features of Resistive RAM Compute-in-Memory Macros
by Tom Dillinger on 03-02-2021 at 8:00 am
Categories: Events, Foundries, TSMC
5 Comments

Resistive RAM (ReRAM) technology has emerged as an attractive alternative to embedded flash memory storage at advanced nodes. Indeed, multiple foundries are offering ReRAM IP arrays at 40nm nodes, and below.

ReRAM has very attractive characteristics, with one significant limitation:

nonvolatile
long retention time
extremely dense (e.g., 2x-4x density of SRAM)
good write cycle performance (relative to eFlash)
good read performance

but with

limited endurance (limited number of ‘1’/’0’ write cycles)

These characteristics imply that ReRAM is well-suited for the emerging interest in compute-in-memory architectures, specifically for the multiply-accumulate (MAC) computations that dominate the energy dissipation in neural networks.

To implement a trained NN for inference applications, node weights in the network would be written to the ReRAM array, and the data inputs would be (spatially or temporally) decoded as the word lines accessing the array weight bits. The multiplicative product of the data/wordline = ‘1’ and the stored weight_bit = ‘1’ would result in significant memory bitline current that could be readily sensed to denote the bit product output – see the figure below.

At the recent International Solid State Circuits Conference (ISSCC), researchers from Georgia Tech University and TSMC presented results from an experimental compute-in-memory design using TSMC’s 40nm ReRAM macro IP. [1] Their design incorporates several unique features – this article summarizes some of the highlight of their presentation.

Background

As the name implies, ReRAM technology is based on the transitions of a thin film material between a high-resistance and low-resistance state. Although there are a large number of different types of materials (and programming sequences) used, a typical metal-oxide thin-film implementation is depicted in the figure below.

The metal oxide thin film material shown incorporates the source and transport of oxygen ions/vacancies under an applied electric field of high magnitude. (The researchers didn’t elaborate on the process technology in detail, but previous TSMC research publications on ReRAM development did utilize a TiO-based thin film programming layer. Multiple metal-oxide thin film materials are also used.)

As depicted in the figure above, an initial “filament forming” cycle is applied, resulting in transport of oxygen ions in the thin film. In the Reset state (‘0’), a high electrical resistance through the metal-oxide film is present. During the application of a Set (‘1’) write cycle, oxygen ion migration occurs, resulting in an extension of the filament throughout the thin film layer, and a corresponding low electrical resistance. In the (bipolar operation) technology example depicted above, the write_0 reset cycle breaks this filament, returning the ReRAM cell to its high resistance state.

The applied electric field across the top thin film for the (set/reset) write operation is of necessity quite large; the applied “read” voltage to sense the (low or high) bitcell resistance utilizes a much smaller electric field.

There are several items of note about ReRAM technology:

the bitcell current is not a strong function of the cell area

The filamentary nature of the conducting path implies that the cell current is not strongly dependent on the cell area, offering opportunities for continued process node scaling.

endurance limits

There is effectively a “wearout” mechanism in the thin film for the transition between states – ReRAM array specifications include an endurance limits on the number of write cycles (e.g., 10**4 – 10**6). Commonly, there is no limit on the number of read cycles.

The endurance constraints preclude the use of ReRAM as a general-purpose embedded “SRAM-like” storage array, but it is the evolutionary approach adopted as an eFlash replacement, and a compute-in-memory offering where pre-calculated weights are written, and updated very infrequently.

resistance ratio, programming with multiple write cycles

The goal of ReRAM technology is to provide a very high ratio of the high resistance to low resistance states (HRS/LRS). When the cell is being accessed during a read cycle – i.e., data/wordline = ‘1’ – the bitline sensing circuit is simplified if i_HRS << i_LRS.

Additionally, it is common to implement a write to the bitcell using multiple iterations of a write-read sequence, to ensure the resulting HRS or LRS cell resistance is within the read operation tolerances. (Multiple write cycles are also initially used during the forming step.)

HRS drift, strongly temperature dependent

The high-resistance state is the result of the absence of a conducting filament in the top thin film, after the oxygen ion transport during a write ‘0’ operation. Note in the figure above the depiction of a high oxygen vacancy concentration in the bottom metal oxide film. Any time a significant material concentration gradient is present, diffusivity of this material may occur, accelerated at higher temperatures. As a result, the HRS resistance will drift lower over extended operation (at high temperature).

Georgia Tech/TSMC ReRAM Compute-in-Memory Features

The researchers developed a ReRAM-based macro IP for a neural network application, with the ReRAM array itself providing the MAC operations for a network node, and supporting circuitry providing the analog-to-digital conversion and the remaining shift-and-add logic functionality. The overall implementation also incorporated three specific features to address ReRAM technology issues associated with: HRS and LRS variation; low (HRS/LRS) ratio; and, HRS drift.

low HRS/LRS ratio

One method for measuring the sum of the data inputs to the node multiplied times a weight bit is to sense the resulting bitline current drawn by the cells whose data/wordline = ‘1’. (Note that unlike a conventional SRAM block with a single active decoded address wordline, the ReRAM compute-in-memory approach will have an active wordline for each data input to the network node whose value is ‘1’. This necessitates considerable additional focus on read-disturb noise on adjacent, unselected rows or the array.) However, for a low HRS/LRS ratio, the bitline current contribution from cells where data = ‘1’ and weight = ‘0’ needs to be considered. For example, if (HRS/LRS) = 8, the cumulative bitline current of eight (data = ‘1’ X weight = ‘0’) products will be equivalent to one LRS current (‘1’ X ‘1’), a binary multiplication error.

The researchers chose to use an alternative method. Rather than sensing the bitline current (e.g., charging a capacitor for a known duration to develop a readout voltage), the researchers pumped a current into the active bitcells and measured Vbitline directly, as illustrated below.

The effective resistance is the parallel combination of the active LRS and HRS cells. The unique feature is that the current source value is not constant, but is varied with the number of active wordlines – each active wordline also connects to an additional current source input. Feedback from Vbitline to each current source branch is also used, as shown below.

This feedback loop increases the sensitivity of each current source branch to Reffective, thus amplifying the resistance contribution of each (parallel) LRS cell on the bitline, and reducing the contribution of each (parallel) HRS cell. The figure below illustrates how the feedback loop fanout to each current branch improves the linearity of the Vbitline response, with an increasing number of LHS cells accessed (and thus, parallel LRS resistances contributing to Rtotal).

LRS/HRS variation

As alluded to earlier, multiple iterations of write-read are often used, to confirm the written value into the ReRAM cell.

The technique employed here to ensure a tight tolerance on the written HRS and LRS value evaluates the digital value read after the write, and increases/decreases the pulse width of the subsequent (reset/set) write cycle iteration until the (resistance) target is reached, ending the write cycle.

HRS drift

The drift in HRS resistance after many read cycles is illustrated below (measured at high operating conditions to accelerate the mechanism).

To compensate for the drift, each bitcell is periodically read – any HRS cell value which has changed beyond a pre-defined limit will receive a new reset write cycle to restore its HRS value. (The researchers did not discuss whether this “mini-reset” HRS write cycle has an impact on the overall ReRAM endurance.)

Testsite Measurement Data

A micrograph of the ReRAM compute-in-memory testsite (with specs) is shown below.

Summary

ReRAM technology offers a unique opportunity for computing-in-memory architectures, with the array providing the node (data * weight) MAC calculation. The researchers at Georgia Tech and TSMC developed a ReRAM testsite with additional features to address some of the technology issues:

HRS/LRS variation: multiple write-read cycles with HRS/LRS sensing are used
low HRS/LRS ratio: a Vbitline voltage-sense approach is used, with a variable bitline current source (with high gain feedback)
HRS drift: bitcell resistance is read periodically, and a reset write sequence applied if the read HRS value drops below a threshold

I would encourage you to review their ISSCC presentation.

-chipguy

References

[1] Yoon, Jong-Hyeok, et al., “A 40nm 64kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification”, ISSCC 2021, paper 29.1.

March 1, 2021March 10, 2021

TSMC ISSCC 2021 Keynote Discussion

TSMC ISSCC 2021 Keynote Discussion
by Daniel Nenni on 03-01-2021 at 6:00 am
Categories: Events, Foundries, TSMC
6 Comments

Now that semiconductor conferences are virtual there are better speakers since they can prerecord and we have the extra time to do a better job of coverage. Even when conferences go live again I think they will also be virtual (hybrid) so our in depth coverage will continue.

ISSCC is one of the conferences we covered live since it’s in San Francisco so that has not changed. We will however be able to cover many more sessions as they come to our homes on our own time.

First off is the keynote by TSMC Chairman Mark Liu: Unleashing the Future of Innovation:

Given the pandemic related semiconductor boom that TSMC is experiencing, Mark might not have had time to do a live keynote so this was a great opportunity to hear his recorded thoughts on the semiconductor industry, the foundry business model, and advanced semiconductor technologies. Here are some highlights from his presentation/paper intermixed with my expert insights:

The semiconductor industry has been improving transistor energy efficiency by about 20-30% for each new technology generation and this trend will continue.
The global semiconductor market is estimated at $450B for 2020.
Products using these semiconductors represent 3.5% of GPD ($2T USD).
From 2000 to 2020 the overall semiconductor industry grew at a steady 4%.
The fabless sector grew at 8% and foundry grew 9% compared to IDM at 2%.
In 2000 fabless revenue accounted for 17% of total semiconductor revenue (excluding memory).
In 2020 fabless revenue accounted for 35% of total semiconductor revenue (excluding memory).
Unlike IDMs, innovators are only limited by their ideas not capital.

Nothing like a subtle message to the new Intel CEO. It will be interesting to see if the Intel – TSMC banter continues. I certainly hope so. The last one that started with Intel saying that the fabless model was dead did not end so well.

Mark finished his IDM message with:

“Over the previous five decades, the most advanced technology had been available first to captive integrated device manufacturers (IDMs). Others had to make do with technologies that were one or several generations behind. The 7nm logic technology (mass production in 2017) was a watershed moment in semiconductor history. In 2017, 7nm logic, was the first time that the world’s most advanced technology was developed and delivered by a pure-play foundries first, and made available broadly to all fabless innovators alike. This trend will likely continue for future technology generations…”

As we all now know Intel will be expanding TSMC outsourcing at 3nm. TSMC 3nm will start production in Q4 of this year for high volume manufacturing beginning in 2H 2022. The $10B question is: Will Intel get the Apple treatment from TSMC (early access, preferred pricing, and custom process recipes)?

I’m not sure everyone understands the possible ramifications of Intel outsourcing CPU/GPU designs to TSMC so let’s review:

Intel and AMD will be on the same process so architecture and design will be the focus. More direct comparisons can be made.
Intel will have higher volumes than AMD so pricing might be an issue. TSMC wafers cost about 20% less than Intel if you want to do the margins math.
Intel will have designs on both Intel 7nm and TSMC 3nm so direct PDK/process comparisons can be made.

Bottom line: 2023 will be a watershed moment for Intel manufacturing, absolutely!

February 14, 2021April 26, 2022

How SerDes Became Key IP for Semiconductor Systems

How SerDes Became Key IP for Semiconductor Systems
by Eric Esteve on 02-14-2021 at 10:00 am
Categories: IP, IPnest, Semiconductor Services, TSMC

We have seen that the interface IP category is seeing incredibly high growth rate over the last two decades and we expect this category to generate an ongoing high source of IP revenues for at least another decade. But if we dig into the various successful protocols like PCI Express, Ethernet or USB, we can detect a common function in the Physical (PHY) part, the Serializer/Deserializer (SerDes) function.

In 1998, advanced interconnects used in telecom application were based on 622 MHz LVDS I/O. Telecom chip makers were building huge chips integrating 256 LVDS I/O running at 622 MHz to support Networking fabric. Today, advanced PAM4 SerDes run at 112 Gbps; over a single connection to support 100G Ethernet. In twenty years, SerDes technology efficiency jumped by a factor of 180-times! If we make a quick comparison with CPU technologies. In 1998 Intel released the Pentium II Dixon processor, whose frequency was 300 MHz. In 2018, an Intel Core i3 run at 4 GHz. CPU frequencies have grown by a factor of 15 times over a span of twenty years while SerDes speeds have exploded by by a factor of 180-times.

SerDes are now used in many more application than just telecom, to interface chips and systems. At the end of the 2000’s, smartphones integrated USB3, SATA and HDMI interfaces, while Telecom and PC/server integrated both PCIe and Ethernet. These trends resulted in the interface IP market to become a sizeable IP category growing above $200 million at that time. It was small compared to the CPU category, which was four or five times larger. But, since 2010, the interface category has seen at least 15%, year over year. It was the fastest growing category compared with all other semiconductor IP categories, such as CPU, GPU, DSP, Library, etc. The reason is directly linked with the number of connected devices growing every year, each exchanging more data (more movie, pictures, etc.). Connectivity is the beginning of the chain of communication, to the internet modem or base station, Ethernet switch and the datacenter network.

Figure 1: Long Term Ethernet Switch Forecast (source: Dell’Oro)

During the 2010 decade the worldwide community became almost completely connected. Ethernet became the backbone of this connectivity as both the connectivity rates and the number of datacenter quickly increased over the decade. If we use SerDes rates as an indicator, it was 10 Gbps in 2010, 28 Gbps in 2013 and 56 Gbps in 2016 (allowing to support 10G, 25G and 50G Ethernet resp.) and 112 Gbps in 2019.

Then, in 2017, the exploding high-speed connectivity needs for emerging data-intensive compute applications such as machine learning and neural networks started to appear, adding to the growing need of high bandwidth connectivity. At the same time, analog mixed-signal architectures, which were the norm for SerDes design since the inception, became extremely difficult to manage and much more sensitive to process, voltage, and temperature variations, due to the evolution of CMOS technology toward advanced FinFET. In modern nanometer FinFET technologies, building transistors involves stacking individual electrons, given the tiny dimensions of the transistors. Thus, the construction of precise, analog circuits that can sustain stressful environmental variations is extremely difficult.

But the positive point with advanced technology like 7nm is that you can integrate an incredible number of transistors by sq. mm (density of 100 million Transistor per sq. mm), so it’s now possible to develop new digital-based architecture leveraging Digital Signal Processing (DSP) to do the vast majority of the Physical Layer work. DSP-based architecture enables the use of higher order Pulse Amplitude Modulation (PAM) modulation scheme compared to Non-Return to Zero (NRZ or PAM2) used by historical previous analog mixed-signal approaches. PAM 4 enabled doubling data throughput of channels without having to increase the bandwidth of channels themselves. As an example, a channel with 28 GHz of bandwidth can support a maximum data throughput of 56 Gbps using NRZ signaling. With the use of PAM-4 DSP technique this same 28 GHz bandwidth channel can now support a data rate of 112 Gbps! When you consider that analog SerDes architectures are limited to a maximum of 56 Gbps rates for physical reasons (and maybe less…), DSP SerDes are the approach to scale rates to 200 Gbps and beyond, with the use of more sophisticated modulation schemes (eg. PAM-6 or PAM-8).

Using DSP based SerDes is not only required for building robust interfaces in FinFET technologies, but it is also the only way to double data rates for above 56 Gbps, eg. 112 Gbps with PAM-4, 200 Gbps with PAM-8. And this need for more bandwidth is the requirement linked with emerging data-intensive applications like AI (to interconnect CPU and accelerator), ADAS, and to follow the data-centric trend of the connected human community, expected to grow steadily over the next decade.

Figure 2: Top 5 Interface IP Forecast & CAGR (source: IPnest 2020)

In the “Interface IP Survey” IPnest rank the market share of IP vendor revenues by protocol since 2009. In the 2020 version of the report, we have shown that the Interface IP category will have 15% CAGR from 2020-2024 to reach $1.57 billion, as listed in Figure 2. This is a wide IP market including PCIe, Ethernet and SerDes as well as USB, MIPI, HDMI, SATA and memory controller IP. In 2019, Synopsys is a strong leader with 53% market share of the estimated $870 million IP market, followed by Cadence with 12%. Both EDA companies have defined a one-stop-shop business model, addressing the mainstream market. This strategy is successful for these large companies as it targets a wide part of various segments (smartphone, consumer, automotive or datacenter), but not the most demanding high-end portion of these segments.

Nevertheless, another strategy can be successful for the IP market, which is to strongly focus on one segment (eg. High-end) of the market and provide the best experience to very demanding hyperscalar customers. If you can build an excellent engineering team able to develop top quality products on the most advanced technologies, focusing on the high end of the market, the resulting business model can be rewarding.

We have seen that SerDes IP is the key to the interface IP market. Furthermore if we concentrate on PCIe and Ethernet protocols, Figure 3 illustrates the IP revenues forecast 2020-2025, limited to high-end PCIe (Gen 5 and Gen 6) and high-end Ethernet (PHY based on 56G, 112G and 224G SerDes), including D2D protocol for a reason that will be describes shortly.

Figure 3: High-End Interface IP Forecast & CAGR (source: IPnest 2021)

This high-end interface IP forecast show 28% CAGR from 2020-2025 (to be compared with 15% for the total interface IP market), and a TAM of $806 million in 2025. One young company has demonstrated strong leadership on this High-End interface IP segment, thanks to their focus on high-end SerDes (112G since 2017 and soon 200G) targeting the most advanced technology nodes (7nm in 2017, then 5nm in 2019) offered by the two leading foundries, TSMC and Samsung. Alphawave, was founded in 2017 has are rumored to have $75 million in orders in 2020, thanks to their positioning targeting the most advanced rates and application of the high-end segment of PCIe and Ethernet. In this portion of the market, they enjoyed 28% market share in 2019 and 36% in 2020. If Alphawave can keep their advance on the high-end SerDes market, it’s not unrealistic to foresee $300-400 million in IP revenues… by 2024-2025!

Since 2019, a new sub-segment, D2D interface, has emerged and is expected to grow with 46% CAGR from 2020-2024. By definition, D2D protocol are used between two chips or die, within a common silicon package. Briefly, we consider two cases for D2D: i) dis-integration of the master SoC to avoid SoC area to badly impact yield or become larger that the maximum reticle size, or ii) SoC interconnect with “service” chiplet (can be I/O chip, FPGA, accelerator…).

At this point (February 2021), there are several protocols being used, with the industry trying to build formalized standards for many of them. Current leading D2D standards includes i) Advanced Interface Bus (AIB, AIB2) initially defined by Intel who has offered royalty free usage, ii) High Bandwidth Memory (HBM) where DRAM dies are stacked on each other on top of a silicon interposer and are connected using TSVs, iii) Domain-Specific Architecture (ODSA) subgroup, an industry group, has defined two other interfaces, Bunch of Wires (BoW) and OpenHBI. All of these D2D standards are based on DDR-like protocol, a parallel group of single-ended data wires being accompanied with a forwarded clock currently operating in the the 2GHz to 4 GHz range. By using literally hundred of parallel wires over very short distances, these interfaces compete with VHS SerDes NRZ, usually defined around 40 Gbps, and offering a strong advantage to enable a much lower latency and lower power consumption, compared to SerDes.

There is now consensus in the industry that a maniacal focus on achieving Moore’s law is becoming not valid anymore for advanced technology node, eg. 7nm and below. Chip integration is still happening, with more transistor being added per sq. mm at every new technology node. However, the cost per transistor is growing higher every new node. Chiplet technology is a key initiative to drive increased integration for the main SoC while using older mainstream nodes for service chiplet. This hybrid strategy decreases both the cost and the design risk associated with integration of the service IP directly into the main SoC. IPnest believes this trend will have two main effect in the interface IP business, one will be the strong growth of D2D IP revenues soon (2021-2025), and the other is the creation of the heterogenous chiplet market to augment the high end SerDes IP market.

We have forecasted the growth of the D2D Interface IP category for 2020-2025, passing from less than $10 million in 2020 to $171 million in 2025 (87% CAGR). This forecast is based on the assumption that the service chiplet market should explode in 2023, when most of advanced SoC will be designed in 3nm. This will make integration of high-end IP like SerDes far too risky, leading to externalizing this functionality into a chiplet designed in more mature node like 7 or 5nm. If Interface IP vendors will be major actors in this revolution, the Silicon foundries addressing the most advanced nodes like TSMC and Samsung and manufacturing the main SoC will have key role. We don’t think they will design chiplet, but they could make the decision to support IP vendors and push them to design chiplet to be used with SoC in 3nm, like they do today when supporting advanced IP vendors to market their high-end SerDes as hard IP in 7nm and 5nm. Intel’s recent transition to 3^rd party foundries is expected to also leverage third party IPs, as well as heterogenous chiplet adoption by the semiconductor heavyweight. In this case, no doubt that Hyperscalars like Microsoft, Amazon and Google will also adopt chiplet architecture… if they don’t even precede Intel in chiplet adoption.

By Eric Esteve (PhD.) Analyst, Owner IPnest

Also Read:

Interface IP Category to Overtake CPU IP by 2025?

Design IP Revenue Grew 5.2% in 2019, Good News in Declining Semi Market

#56thDAC SerDes, Analog and RISC-V sessions

February 7, 2021March 26, 2023

Will EUV take a Breather in 2021?

Will EUV take a Breather in 2021?
by Robert Maire on 02-07-2021 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services, TSMC
6 Comments

-KLAC- Solid QTR & Guide but flat 2021 outlook
-Display down & more memory mix
-KLAC has very solid Dec Qtr & guide but 2021 looks flattish
-Mix shift to memory doesn’t help- Display weakness
-Despite flat still looking at double digit growth
-EUV driven business may see some slowing from digestion

As always, KLAC came in at the high end of the guided range with revenues of $1.65B and non GAAP EPS of $3.24 versus the guided range of $2.82 to $3.46. Guidance is for $1.7B +-75M and non GAAP EPS range of $3.23 – $3.91. By all financial and performance metrics a very solid quarter

A “flattish” 2021 while WFE grows “mid teens”

Management suggested that WFE which exited 2020 at $59-$60B would grow double digits in 2021 but the year would look a bit more flat for KLAC as its acquired display group is expected to shrink and there is an expected mix shift towards memory which is less process control intensive.

Foundry has been strong which has been very good for KLA and the current quarter is expected to see roughly 68% of business from foundry

Will EUV take a breather?

KLA obviously sells process management tools to companies working on new process such as EUV. TSMC has bought so many EUV tools it probably has problems finding the space for more. TSMC has also clearly gone well over the hump of getting EUV to work and likely may not need as much process control and maybe could slow its EUV scanner purchases a bit given that its so far ahead.

Intel is obviously still coming up the learning curve and purchasing curve and Samsung is in between the two. We would not expect either Samsung nor Intel to be as EUV intensive as TSMC has been, at least not in the near term. All this being said , it is not unreasonable to expect EUV related process management to slow slightly.

Memory not as intensive as Foundry/logic

The industry is expecting memory makers to increase capex spend in 2021 as supply and demand have been in reasonable balance and supply is expected to get tighter.

Most of the expectation is on the DRAM side which is slightly less process control intensive as compared to NAND and likely lower in overall spend. This mix shift towards memory is obviously better for memory poster child Lam than for foundry poster child KLA. However its not like foundry is falling off a cliff with TSMC spending a record of between $26B and $28B in capex.

Service adding nice recurring revenue

As we have seen with KLA’s competitors, the service business continues its rise in importance to the company. The recurring revenue stream counterbalances the new equipment cyclicality and lumpiness. Having 25% or more of your revenue coming from service is very attractive

Wafer inspection positive while reticle inspection negative

EUV “print check” has obviously been very good for KLA and a way to play the EUV transition given the issues in reticle inspection. Patterning (AKA reticle inspection) was down significantly after a nice bump in prior quarters where KLA managed to take back some business from Lasertec (which now sports a $10B Mkt Cap).

Obviously “missing the boat” on EUV reticle inspection is toothpaste that can’t be put back in the tube. We expect Lasertec to get the lions share of Intel’s business as it ramps up EUV.

The stock

If we assume roughly $7B in revenues for 2021 ($1.75B/Q) with roughly $15 in EPS ($3.75/Q) we arrive at roughly 19X forward EPS, at the current stock price. This is likely a pretty good valuation for a company with stellar/flawless execution in a slowing, but still strong, market.

Investors will likely get turned off by the “flattish” commentary despite the good numbers. It also doesn’t help that the chip stocks have been feeling a bit like they are turning over here Despite any weakness KLA remains the top financial performer in the industry.

Also Read:

New Intel CEO Commits to Remaining an IDM

ASML – Strong DUV Throwback While EUV Slows- Logic Dominates Memory

2020 was a Mess for Intel

December 22, 2020February 5, 2021

A Research Update on Carbon Nanotube Fabrication

A Research Update on Carbon Nanotube Fabrication
by Tom Dillinger on 12-22-2020 at 10:00 am
Categories: Events, Foundries, TSMC

It is quite amazing that silicon-based devices have been the foundation of our industry for over 60 years, as it was clear that the initial germanium-based devices would be difficult to integrate at a larger scale. (GaAs devices have also developed a unique microelectronics market segment.) More recently, it is also rather amazing that silicon field-effect devices have found a new life, through the introduction of topologies such as FinFETs, and soon, as nanosheets. Research is ongoing to bring silicon-based complementary FET (CFET) designs to production status, where nMOS and pMOS devices are fabricated vertically, eliminating the lateral n-to-p spacing in current cell designs. Additionally, materials engineering advances have incorporated (tensile and compressive) stress into the silicon channel crystal structure, to enhance free carrier mobility.

However, the point of diminishing returns for silicon engineering is approaching:

silicon free carrier mobility is near maximum, due to velocity saturation at high electric fields
the “density of free carrier states” (DoS) at the conduction and valence band edges of the silicon semiconductor is reduced with continued dimensional scaling – more energy is required to populate a broader range of carrier states
statistical process variation associated with fin patterning is considerable
heat conduction from the fin results in increased local “self-heat” temperature, impacting several reliability mechanisms (HCI, electromigration)

A great deal of research is underway to evaluate the potential for a fundamentally different field-effect transistor material than silicon, yet which would also be consistent with current high volume manufacturing operations. One option is to explore monolayer, two-dimensional semiconducting materials for the device channel, such as molybdenum disulfide (MoS2).

Another promising option is to construct the device channel from carbon nanotubes (CNT). The figure below provides a simple pictorial of the unique nature of carbon bonding. (I’m a little rusty on my chemistry, but I recall “sp2” bonding refers to the pairing of electrons from adjacent carbon atoms from a sub-orbital “p shell” around the nucleus. There are no “dangling bonds”, and the carbon material is inert.)

Note that graphite, graphene, and CNT structures are similar chemically – experimental materials analysis with graphite is easier, and can ultimately be extended to CNT processing.

At the recent IEDM conference, TSMC provided an intriguing update on their progress with CNT device fabrication. [1] This article summarizes the highlights of that presentation.

CNT devices offer some compelling features:

very high carrier mobility (> 3,000 cm**2/V-sec, “ballistic transport”, with minimal scattering)
very thin CNT body dimensions (e.g., diameter ~1nm)
low parasitic capacitance
excellent thermal conduction
low temperature (<400C) processing

The last feature is particularly interesting, as it also opens up the potential for integration of silicon-based, high-temperature fabrication with subsequent CNT processing.

Gate Dielectric

A unique process flow was developed to provide the “high K” dielectric equivalent gate oxide for a CNT device, similar to the HKMG processing of current silicon FETs.

The TEM figure above illustrates the CNT cross-section. Deposition of an initial interface dielectric (Al2O3) is required for compatibility with the unique carbon surface – i.e., suitable nucleation and conformity of this thin layer on carbon are required.

Subsequently, atomic level deposition (ALD) of a high-K HfO2 film is added. (These dielectric experiments on material properties were done with a graphite substrate, as mentioned earlier.)

The minimum thicknesses of these gate dielectric layers is constrained by the requirement for very low gate leakage current – e.g., <1 pA/CNT, for a gate length of 10nm. The test structure fabrication for measuring gate-to-CNT leakage current is illustrated below. (For these electrical measurements, the CNT structure used a quartz substrate.)

The “optimal” dimensions from the experiments results in t_Al2O3 = 0.35nm and t_HfO2 = 2.5nm. With these extremely thin layers, Cgate_ox is very high, resulting in improved electrostatic control. (Note that these layers are thicker than the CNT diameter, the impact of which will be discussed shortly.)

Gate Orientation

The CNT devices evaluated by TSMC incorporated a unique “top gate plus back gate” topology.

The top gate provides the conventional semiconductor field-effect device input, while the (larger) back gate provides electrostatic control of the carriers in the S/D extension regions, to effectively reduce the parasitic resistances Rs and Rd. Also, the back gate influences the source and drain contact potential between the CNT and Palladium metal, reducing the Schottky diode barrier and associated current behavior at this semiconductor-metal interface.

Device current

The I-V curves (both linear and log Ids for subthreshold slope measurement) for a CNT pFET are depicted below. For this experiment, Lg = 100nm, 200nm S/D spacing, CNT diameter = 1nm, t_Al2O3 = 1.25nm, t_HfO2 = 2.5nm.

For this test vehicle (fabricated on a quartz substrate), a single CNT supports Ids in excess of 10uA. Further improvements would be achieved with thinner dielectrics, approaching the target dimensions mentioned above.

Parallel CNTs in production fabrication will ultimately be used – the pertinent fabrication metric will be “the number of CNTs per micron”. For example, a CNT pitch of 4nm would be quoted as “250 CNTs/um”.

Challenges

There are certainly challenges to address when planning for CNT production (to mention but a few):

regular/uniform CNT deposition, with exceptionally clean surface for dielectric nucleation
need to minimize the carrier “trap density” within the gate dielectric stack
optimum S/D contact potential materials engineering
device modeling for design

The last challenge above is especially noteworthy, as current compact device models for field-effect transistors will definitely not suffice. The CNT gate oxide topology is drastically different than a planar or FinFET silicon channel. As the gate-to-channel electric field is radial in nature, there is not a simple relation for the “effective gate oxide”, as with a planar device.

Further, the S/D extensions require unique Rs and Rd models. Also, the CNT gate oxide is thicker than the CNT diameter, resulting in considerable fringing fields from the gate to the S/D extensions and to the (small pitch separated) parallel CNTs. Developing suitable compact models for CNT-based designs is an ongoing effort.

Parenthetically, a CNT “surrounding gate” oxide – similar to the gate-all around nanosheet – would be an improvement over the deposited top gate oxide, but difficult to manufacture.

TSMC is clearly investing significant R&D resources, in preparation for the “inevitable” post-silicon device technology introduction. The results on CNT fabrication and electrical characterization demonstrate considerable potential for this device alternative.

-chipguy

References

[1] Pitner, G., et al, “Sub-0.5nm Interfacial Dielectric Enables Superior Electrostatics: 65mV/dec Top-Gated Carbon Nanotube FETs at 15nm Gate Length”, IEDM 2020.

December 16, 2020January 11, 2022

Advanced Process Development is Much More than just Litho

Advanced Process Development is Much More than just Litho
by Tom Dillinger on 12-16-2020 at 10:00 am
Categories: Events, Foundries, Lithography, TSMC
1 Comment

The vast majority of the attention given to the introduction of each new advanced process node focuses on lithographic updates. The common metrics quoted are the transistors per mm**2 or the (high-density) SRAM bit cell area. Alternatively, detailed decomposition analysis may be applied using transmission electron microscopy (TEM) on a lamella sample, to measure fin pitch, gate pitch, and (first-level) metal pitch.

With the recent transition of the critical dimension layers from 193i to extreme ultraviolet (EUV) exposure, the focus on litho is understandable. Yet, process development and qualification encompasses many more facets of materials engineering to achieve robust manufacturability, so that the full complement of product goals can be achieved. Specifically, process development engineers are faced with increasingly stringent reliability targets, while concurrently achieving performance and power dissipation improvements.

At the recent IEDM conference, TSMC gave a technical presentation highlighting the development focus that enabled the N5 process node to achieve (risk production) qualification. This article summarizes the highlights of that presentation. [1]

An earlier SemiWiki article introduced the litho and power/performance features of N5. [2] One of the significant materials differences in N5 is the introduction of a “high mobility” device channel, or HMC. As described in [2], the improved carrier mobility in N5 is achieved by the introduction of additional strain on the device channel region. (Although TSMC did not provide technical details, the pFET hole mobility is also likely improved by the introduction of a moderate percentage of Germanium into the Silicon channel region, or Si(1-x)Ge(x).)

Additionally, the optimized N5 process node incorporates an optimized high-K metal-gate (HKMG) dielectric stack between gate and channel, resulting in a stronger electric field.

A very significant facet of this “bandgap engineering” for carrier mobility and the gate oxide stack materials selection is to ensure that reliability targets are satisfied. Several of the N5 reliability qualification results are illustrated below.

TSMC highlighted the following reliability measures from the N5 qualification test vehicle:

bias temperature stability (BTI)
both NBTI for pFETs and PBTI for nFETs, manifesting in a performance degradation over time from a device Vt shift (positive absolute value) due to trapped oxide charge
also may result in a degradation of VDDmin for SRAM operation
hot carrier injection (HCI)
an asymmetric injection of charge into the gate oxide near the drain end of the device (operating in saturation), resulting in degraded carrier mobility
time-dependent gate oxide dielectric breakdown (TDDB)

Note that the N5 node is targeted to satisfy both high-performance and mobile (low-power) product requirements. As a result, both performance degradation and maintaining an aggressive SRAM VDDmin are important long-term reliability criteria.

TDDB

The figure above illustrates that the TDDB lifetime is maintained relative to node N7, even with the increased gate electric field.

Self-heating

The introduction of FinFET device geometries substantially altered the thermal resistance paths from the channel power dissipation to the ambient. New “self-heating” analysis flows were employed to more accurately calculate local junction temperatures, often displayed as a “heat map”. As might be expected with the aggressive dimensional scaling from N7 to N5, the self-heat temperature rise is greater in N5, as illustrated below.

Designers of HPC products need to collaborate with both their EDA partners for die thermal analysis tools and their product engineering team for accurate (on-die and system) thermal resistance modeling. For the on-die model, both active and inactive structures strongly influence the thermal dispersion.

HCI

Hot carrier injection performance degradation for N7 and N5 are shown below, for nFETs and pFETs.

Note that HCI is strongly temperature-dependent, necessitating accurate self-heat analysis.

BTI

The pMOS NBTI reliability analysis results are illustrated below, with the related ring oscillator performance impact.

In both cases, reliability analysis demonstrates improved BTI characteristics of N5 relative to N7.

SRAM VDDmin

The SRAM minimum operating voltage (VDDmin) is a key parameter for low-power designs, especially with the increasing demand for local memory storage. Two factors that contribute to the minimum SRAM operating voltage (with sufficient read and write margins) are:

the BTI device shift, as shown above
the statistical process variation in the device Vt, as shown below (normalized to Vt_mean in N7 and N5)

Based on these two individual results, the SRAM reliability data after HTOL stress shows improved VDDmin impact for N5 versus N7.

Interconnect

TSMC also briefly described the N5 process engineering emphasis on (Mx, low-level metal) interconnect reliability optimization. With an improved damascene trench liner and a “Cu reflow” step, the scaling of the Mx pitch – by ~30% in N5 using EUV – did not adversely impact electromigration fails, nor line-to-line dielectric breakdown. The figure below illustrates the line-to-line (and via) cumulative breakdown reliability fail data for N5 compared to N7 – N5 tolerates the higher electric field with the scaled Mx pitch.

Summary

The majority of the coverage associated with the introduction of TSMC’s N5 process node related to the broad adoption of EUV lithography to replace multipatterning for the most critical layers, enabling aggressive area scaling. Yet, process engineers must also optimize materials selection and many individual fabrication steps, to achieve reliability targets. TSMC recently presented how these reliability measures for N5 are superior to prior nodes.

-chipguy

References

[1] Liu, J.C., et al, “A Reliability Enhanced 5nm CMOS Technology Featuring 5th Generation FinFET with Fully-Developed EUV and High Mobility Channel for Mobile SoC and High Performance Computing Application”, IEDM 2020.

[2] https://semiwiki.com/semiconductor-manufacturers/tsmc/282339-tsmc-unveils-details-of-5nm-cmos-production-technology-platform-featuring-euv-and-high-mobility-channel-finfets-at-iedm2019/

Design Considerations for 3DICs

Design Considerations for 3DICs
by Tom Dillinger on 12-14-2020 at 6:00 am
Categories: Events, Foundries, TSMC
3 Comments

The introduction of heterogeneous 3DIC packaging technology offers the opportunity for significant increases in circuit density and performance, with corresponding reductions in package footprint. Yet, the implementation of a complex 3DIC product requires a considerable investment in methodology development for all facets of the design:

system architecture partitioning (among die)
I/O assignments for all die, both for signals and the power distribution network (PDN)
die floorplanning, driven by the I/O assignments
probe card design (with potential reuse between individual die and 3DIC assembly)
critical timing path analysis, assessing the tradeoffs between timing paths on-die versus the implementation of vertical paths between stacked die
IR drop analysis, a key facet of 3DIC planning due to the power delivery to stacked die using through-silicon or through-dielectric vias
a DFT architecture, suitable for 3DIC testing using individual known good die (KGD)
reliability analysis of the composite multi-die thermal package model
LVS physical verification of the multi-die connectivity model

Whereas 2.5D IC packaging technology has pursued “chiplet-based” die functionality (and potential electrical interface connectivity standards), the complexity of 3DIC implementations requires early and extensive investment in the design and analysis flows listed above – a higher risk than 2.5D IC implementations, for sure, but with a potentially greater reward.

At the recent IEDM 2020 conference, TSMC presented an enlightening paper describing their recent efforts to tackle these 3DIC implementation tradeoffs, using a very interesting testchip implementation. This article summarizes the highlights of their presentation. [1]

SoIC Packaging Technology

Prior to IEDM, TSMC presented their 3DIC package offering in detail at their Technology Symposium – known as “System on Integrated Chip”, or SoIC (link).

A (low-temperature) die-to-die bonding technology provides the electrical connectivity and physical attach between die. The figure below depicts available die attach options – i.e., face-to-face, face-to-back, and a complex combination including side-to-side assembly potentially integrating other die stacks.

For the face-to-face orientation, the backside of the top die receives the signal and PDN redistribution layers. Alternatively, a third die on the top of the SoIC assembly may be used to implement the signal and PDN redistribution layers to package bumps – a design testcase from TSMC using the triple-stack will be described shortly.

A through-silicon via (TSV) in die #2 provides electrical connectivity for signals and power to die #1. A through-dielectric via (TDV) is used for connectivity between the package and die #1 in the volumetric region outside of the smaller die #2.

Planning of the power delivery to the SoIC die requires consideration of several factors:

estimated power of each die (especially where die #1 is a high-performance, high-power processing unit)
TSV/TDV current density limits
distinct power domains associated with each die

The figure below highlights the design option of “number of TSVs per power/ground bump”. To reduce IR drop and observe current density limits through a TSV, an array of TSVs may be appropriate – as an example, up to 8 TSVs are shown in the figure. (Examples from both FF and SS corners are shown.)

The tradeoff of using multiple, arrayed TSVs is the impact on interconnect density.

As an illustration, TSMC pursued a unique SoIC implementation – a quad-core ARM A72 processor (die #1) where the L2$ cache arrays commonly integrated with each core have been re-allocated to die #2. The CPU die in process node N5 maintains an L3$ array, while the SRAM die in process node N7 contains the full set of L2$ arrays. A third die on top of die #2 provides the redistribution layers. A total of 2700 connections are present between CPU die #1 and the L2$ arrays in die #2.

This is an example of how SoIC technology could have a major impact on system architectures, where a (large) cache memory is connected vertically to a core, rather than integrated laterally on a monolithic die.

PDN Planning

A key effort in the development of an SoIC is the concurrent engineering related to the assignment of bump, pad, and TSV/TDV locations throughout, for both signals and the PDN.

The figures above highlight the series of planning steps to develop the TSV configuration for the PDN – a face-to-face die attach configuration is used as an example. The original “dummy” bond pads between die (for mechanical stability) are replaced with the signal and PDN TDV and TSV arrays. (TSMC also pursued the goal of re-using the probe card, between die #1 testing and the final SoIC testing – that goal influenced the assignment of pad and TSV locations.)

The TSV implementations for the CPU die and SRAM die also need to be carefully chosen so as to meet IR goals, without adversely impacting overall die interconnect density.

LVS

Briefly, TSMC also highlighted the (multi-phase) LVS connectivity verification methodology, and unique DFT architecture selected for this SoIC test vehicle, as depicted below.

DFT

Another major consideration is the DFT architecture for the SoIC, and how connectivity testing will be accomplished using cross-die scan, as illustrated below.

TSMC demonstrated that the resulting (N5 + N7) SoIC design achieved a 15% performance gain (with suitable L2$ and L3$ hit rate and latency assumptions), leveraging a significant reduction in point-to-point distance afforded by the vertical connectivity between die. The package areal footprint for the SoIC is reduced by ~50% from a monolithic 2D implementation.

3D SoIC packaging technology will offer system architects with unique opportunities to pursue design partitioning across vertical die configurations. The density and electrical characteristics of the vertical bond connections may offer improved performance over lateral (monolithic or 2.5D chiplet-based) interconnects. (The additional power dissipation of “lite I/O” driver and receiver cells between die versus on-chip signal buffering is typically small.)

The tradeoff is the investment required to develop the SoIC die floorplans for TSV and TDV vias to provide the requisite signal count and low IR drop PDN. Although 2.5D chiplet-based package offerings have been aggressively adopted, the performance and footprint advantages of a 3DIC are rather compelling. The TSMC test vehicle demonstrated at IEDM will no doubt generate considerable interest.

-chipguy

References

[1] Cheng, Y.-K., et al., “Next-Generation Design and Technology Co-optimization (DTCO) of System on Integrated Chip (SoIC) for Mobile and HPC Applications”, IEDM 2020.

December 7, 2020February 5, 2021

How Intel Stumbled: A Perspective from the Trenches

How Intel Stumbled: A Perspective from the Trenches
by Daniel Nenni on 12-07-2020 at 6:00 am
Categories: FinFET, Foundries, Intel Foundry, TSMC
11 Comments

Bloomberg did an interview with my favorite semiconductor analyst Stacy Rasgon on “How the Number One U.S. Semiconductor Company Stumbled” that I found interesting. Coupled with the Q&A Bob Swan did at the Credit Suisse Annual Technology Conference I thought it would be good content for a viral blog.

Stacy Rasgon and Bob Swan

Stacy Rasgon is an interesting guy and a lot like me when it comes to offering blunt questions, observations, and opinions that sometimes throw people off. As a result, Stacy is not always the first to ask questions during investor calls and sometimes he is not called on at all which is the case for the most recent Intel Call.

Stacy is the Managing Director and Senior Analyst, US Semiconductors, for AB Bernstein here in California. Interestingly, Stacy has a PhD in Chemical Engineering from MIT, not the usual degree for a sell side analyst. Why semiconductors? Stacy did a co-op at IBM TJ Watson Research Center during his post graduate studies and that hooked him.

I thought it was funny back when Brian Krzanich (BK) was CEO of Intel. BK has a Bachelor’s Degree in Chemistry from San Jose State University and he was answering questions by an analyst with a PhD from MIT. The current Intel CEO Bob Swan is a career CFO with an MBA so maybe that explains the communication issues.

In the Bloomberg interview the focus was on the delays in the Intel processes starting with 14nm, 10nm, and now 7nm. Unfortunately they missed the point. In the history of the semiconductor industry leading edge processes were more like wine where in the words of the great Orson Wells “We will sell no wine before its time”. Guided by Moore’s Law, Intel successfully drove down the bumpy process road until FinFETs came along.

The first FinFET Process was Intel 22nm which was the best kept secret in semiconductor history. We don’t know if it was early or late since it was not discussed before it arrived. 14nm followed which was late due to defect density/yield problems. We talked about that on SemiWiki quite and I had a bit of a squabble with BK at a developer conference. I knew 14nm was not yielding and he said it was only to retract that comment at the next investor call. Intel 10nm is probably the most tardy process in the history of Intel and now 7nm is in question as well.

The foundries historically have been 1-2 nodes behind Intel so they got a relative pass on being late with new processes up until 10nm when TSMC technically caught Intel 14nm.

Bottom line: Leading edge processes use new technology and materials which challenges yield from many different directions. This is a very complex business so it’s extremely difficult to predict schedules because “you never know until you know”. So, try as one might, abiding by Moore’s Law in the FinFET era is a fool’s errand, absolutely.

The other major Intel disruption is the TSMC / Apple partnership. Apple requires a new process each year which started at 20nm (iPhone6). As a result TSMC now does half steps with new technologies. At 20nm TSMC introduced double patterning then added FinFETs at 16nm. At 7nm TSMC later introduced limited EUV and called it 7nm+. AT 5nm TSMC implemented full EUV (half steps).

This is a serious semiconductor manufacturing paradigm shift that I call “The Apple Effect” TSMC must have a new process ready for the iProduct launch every year without fail. Which means the process must be frozen at the end of Q4 for production starting in the following Q2. The net result is a serious amount of yield learning which results in shorter process ramps and superior yield.

The other interesting point is that during Bob Swan’s Credit Suisse interview he mentioned the word IDM 33 times emphasizing the IDM advantage over being fabless. Unfortunately this position is a bit outdated. Long gone are the days when fabless companies tossed designs over the foundry wall to be manufactured.

TSMC, for example, has a massive ecosystem of partners and customers who together spend trillions of dollars on research and development for the greater good of the fabless semiconductor ecosystem. There is also an inner circle of partners and customers that TSMC intimately collaborates with on new process development and deployment. This includes Apple of course, AMD, Arm, Applied Materials, ASML, Cadence, and Synopsys just to name a few.

Bottom line: The IDM underground silo approach to semiconductor design and manufacture is outdated. It’s all about the ecosystem and Intel will learn this first hand as they increasingly outsource to TSMC in the coming process nodes.

December 2, 2020September 1, 2024

No Intel and Samsung are not passing TSMC

No Intel and Samsung are not passing TSMC
by Scotten Jones on 12-02-2020 at 6:00 am
Categories: FinFET, Foundries, GAA, Intel Foundry, Samsung Foundry, Semiconductor Services, TechInsights, TSMC
10 Comments

Seeking Alpha just published an article about Intel and Samsung passing TSMC for process leadership. The Intel part seems to be a theme with them, they have talked in the past about how Intel does bigger density improvements with each generation than the foundries but forget that the foundries are doing 5 nodes in the time it takes Intel to do 3. They also make a big deal about Horizontal Nanosheets (HNS) Versus FinFETs and yes that is impressive, but at the end of the day what you deliver for power, performance and area (PPA) is what really matters.

I have written about this before here.

In this article I will briefly review where each company is currently and where I expect them to be over the next five years. I do not want to go into too much detail in this article because I will be presenting on leading edge logic at the ISS conference in January and covering this in more depth then.

Intel

Figure 1 illustrates Intel’s node introductions starting at 45nm. After many nodes on a 2-year cadence Intel slipped to 3 years at 14nm and 5 years at 10nm. 10nm has been particularly bad with yield and performance issues, even today it is hard to get 10nm parts. Intel has recently announced 10+ now known as 10SF (Super Fin). The Super Fin provides a 17-18% performance improvement like a full node. There is also a rumor that Intel is using EUV for M0 and M1 although I have not confirmed this. M0 and M1 on the original 10nm process are the most complex metal pattering scheme I have ever seen so this might make sense for yield reasons.

Figure 1. Intel Node Introductions.

Intel’s 7nm was scheduled for 2021 and was supposed to get Intel back on track. At 7nm they are doing a smaller 2x density improvement and the implementation of EUV was supposed to solve their yield issues, but the process is now delayed until 2022.

Seeking Alpha makes an argument that Intel will be back on a 2 year cadence for their 5nm process, I am not sure I believe this given their 14nm, 10nm and 7nm history but even if they are I don’t think this puts them in the lead as I will describe below.

14nm/16nm

14nm was Intel’s second generation FinFET and they took a big jump in density. Intel’s 14nm process came out in 2014, Samsung’s 14nm process also came out in 2014 and TSMC’s 16nm process came out in 2015. Intel’s 14nm process was significantly denser than Samsung or TSMC’s 14nm/16nm processes.

Foundry 10nm

In 2016 both foundries came out with 10nm processes and they both passed Intel for the process density lead.

Foundry 7nm/Intel 10nm

In 2017 TSMC released their 7nm process moving further ahead of Intel and in 2018 Samsung released their 7nm process also moving further ahead of Intel. In 2019 Intel finally started shipping 10nm and the Intel 10nm process was slightly denser that TSMC or Samsung, but in 2018 TSMC’s 7+ process (half node) and in 2019 Samsung’s 6nm (half node) processes passed Intel 10nm density. Samsung’s 7nm is also notable as the industry’s first process with EUV, although TSMC soon had EUV running on their 7+ process and is in my opinion the EUV leader today, in fact TSMC claims to have half of all EUV systems in the world currently.

Foundry 5nm

In 2019 the foundries started risk starts on 5nm pulling further ahead of Intel. TSMC 5nm took a much bigger density jump than Samsung’s 5nm and they opened a lead over Samsung and Intel. TSMC 5nm also introduced a high mobility channel. 5nm has ramped throughout 2020 and utilizes EUV for more layers than 7nm.

Foundry 3nm/Intel 7nm

Risk starts for foundry 3nm are due in 2021 and TSMC will pull further ahead of both Intel and Samsung. Samsung will introduce the industry’s first HNS and that is a great accomplishment and positions them well for the future, but we expect TSMC’s 3nm process to be much denser with better power and performance.

Intel’s 7nm process is currently expected around 2022 and is slated to be their first EUV based process (although there may be some EUV use on 10nm as discussed above). Based on their announced density improvements and the announced density improvements for TSMC and Samsung we expect Intel 7nm and Samsung 3nm to have similar densities but TSMC will be much denser than either company.

Foundry 2nm/Intel 5nm

If Intel gets back onto a two-year node interval, then Intel 5nm using HNS will be due in 2024. I am not sure I believe that but for the sake of argument I will go with it. There is also a question as to whether Intel even does 5nm, they are looking at outsourcing and depending on how that goes they may not go beyond 7nm and may use foundries.

TSMC’s 2nm node is now expected to be available for risk starts in 2023 and production in 2024. TSMC has said it will be a full node and even with modest density improvements it will be denser than Intel’s 5nm process based on announced density improvements, Intel will likely pass Samsung but not TSMC. This would be Intel and TSMC’s first HNS. Possibly because it would be Samsung’s second generation HNS maybe they will take a bigger density jump but I don’t see them catching TSMC who is taking bigger jumps at both 5nm and 3nm.

Conclusion

The bottom line is Intel may be doing bigger density jumps at each node than the foundries but from the 14nm nodes in 2014 through the Intel 7nm node expected in 2022, the foundries have done 5 full nodes while Intel has done 3 full nodes and TSMC in particular has opened up a big process lead.

Also Read:

Leading Edge Foundry Wafer Prices

VLSI Symposium 2020 – Imec Monolithic CFET

SEMICON West – Applied Materials Selective Gap Fill Announcement