FD-SOI: Samsung Opens the Kimono a Little

Last week there was a meeting of the GSA Analog/Mixed-Signal (AMS) working group. It was completely focused on FD-SOI (I hate that name, especially since FinFET is also fully-depleted. I vote for BoxFETs.) It was a bases loaded meeting with presentations from ST Microelectronics (calling in from France close to midnight), Samsung and GlobalFoundries. That is 3 for 3 of companies that have announced FD-SOI manufacturing.

Here’s the situation. ST got FD-SOI to the commercial manufacturing stage at 28nm. Others, notably IBM, did research in the area (IBM uses partially depleted SOI for its high-end servers, now manufactured by GlobalFoundries, which acquired IBM’s semiconductor business). Samsung announced that they were licensing ST’s process. However, until yesterday, I had not heard much about what the true status was. Then GlobalFoundries announced a 22nm FD-SOI process (actually a family of processes that they market as FDX). The motivation for 22nm was that they wanted a process that was more competitive with 14/16nm FinFET and they wanted to get maximum use out of the existing installed equipment in their Dresden fab. In another wrinkle nothing to do with FD-SOI, GlobalFoundries also licensed Samsung’s 14nm FinFET process.

So on to what Kelvin Low from Samsung said. The main motivation for them to license FD-SOI is that the #1 concern of most customers, and the fastest growing part of the market, is lowest cost per transistor followed closely by low power. People were also concerned with having multiple sources, which had been a problem for ST that Samsung, with its massive manufacturing resources, could help solve. FinFET has a place, obviously, for the leading edge but it delivers high performance but at increased cost, which is the wrong tradeoff for many. FD-SOI involves fewer masks than bulk and about half as many as FinFET (in the front end, the metal stack BEOL is unaffected). Also, the back biasing of FD-SOI is really important. FBB (forward) allows really low voltage operation and RBB (reverse) allows very low leakage standby idle modes. Perfect IoT fodder.

Since this was a mixed-signal working group, Kelvin went into some of the advantages of FD-SOI in the analog RF world. The big advantage of FD-SOI is to be able to use the back-biasing not just to decrease power but add dynamic trimming, gain controlled amplifiers and high gain. Andreia Cathelin of ST had also covered this in her presentation at a level of detail that overwhelmed most of us in the room (certainly me). But the results she had of papers that ST had presented at ISSCC (which I did understand) were undoubtedly impressive. They could do things with FD-SOI that are impossible with bulk (and I think pretty much impossible with FinFET but that is beyond my pay grade).

One thing that I hadn’t realized is that you can run a hybrid process with bulk on some parts of the die (using one extra mask to remove the box) to be able to add ESD structures, BiCMOS options and more. Photomicrograph above.

The current status at Samsung is that wafer level qualification was completed in 2014 and product level reliability in March of this year. PDKs are available. Multiple MPW shuttles are planned (see the graph above for details). The process is currently in its initial ramp, but the base 28nm process of which FD-SOI is a sort of derivative, has alreay run over 2M wafers. The BEOL is completely the same and the FEOL is simpler but still uses the same gate-first HKMG structure.

So what of the future? Things Samsung were not ready to announced (yes, we asked) was what their future process roadmap for FD-SOI would be (22nm, 14nm?). They currently have SRAM, ROM, OTP but are not ready to announce any non-volatile memory option. But you can see some of the directions from the above, Kelvin’s final slide.