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October 14, 2022August 2, 2023 by Daniel Nenni

TSMC 2022 Open Innovation Platform Ecosystem Forum Preview

TSMC 2022 Open Innovation Platform Ecosystem Forum Preview
by Daniel Nenni on 10-14-2022 at 6:00 am
Categories: Events, Foundries, TSMC
5 Comments

One of my favorite events is just around the corner and that is the TSMC OIP Ecosystem Forum and it’s at my favorite Silicon Valley venue the Santa Clara Convention Center. Nobody knows more about the inner workings of the ecosystem than TSMC so this is the premier semiconductor collaboration event, absolutely.

In my 40 years as a semiconductor professional I cannot think of a more exciting time for our industry and TSMC is one of the reasons why. The ecosystem they have built is a force of nature that may never be replicated in the semiconductor industry or any other industry for that matter. Hundreds of thousands of people all working together for a common goal of silicon that could change the world!

The guest speaker for the Silicon Valley event will be none other than Jim Keller of Apple, AMD, Tesla, and Intel fame. Jim is an amazing speaker so you definitely do NOT want to miss this one.

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Learn About:

Emerging advanced node design challenges and corresponding design flows and methodologies for N3/N3E, N4/N4P, N5/N5A, N6/N7, N12e, N22, and 28eF technologies
Latest 3DIC chip stacking and advanced packaging processes, and innovative 3DIC design enablement technologies and solutions targeting HPC and mobile applications
Updated design solutions for specialty technologies enabling ultra-low voltage, analog migration, mmWave RF, and automotive designs targeting automotive and IoT designs
Ecosystem-specific TSMC reference flow implementations, P& R optimization, machine learning to improve design quality and productivity, and cloud-based design solutions
Successful, real-life applications of design technologies and IP solutions from ecosystem members and TSMC customers

For more information on the TSMC OIP Ecosystem Forum, e-mail us at: tsmcevents@tsmc.com.

Here is the agenda as of today:

Time	Plenary Session
08:00 – 09:00	Registration & Ecosystem Pavilion
09:00 – 09:15	Welcome Remarks
09:15 – 10:10	Enabling System Innovation & Guest Speaker
10:10 – 10:30	Coffee Break & Ecosystem Pavilion
	TSMC Technical Talks
10:30 – 11:00	TSMC N3E FinFlex™ Technology: Motivation, Design Challenges, and Solutions TSMC	TSMC 3Dblox™: Unleashing The Ultimate 3DIC Design Productivity TSMC	TSMC Analog Migration Talk TSMC
	HPC & 3DIC Track	Mobile & Automotive Track	IoT, RF & Other Track
11:00 – 11:30	GUC’s 2.5D/3D Chiplets, Interconnect Solutions and Trends GUC	Analog Design Optimization by Integrating MediaTek’s ML-based Engine within the Virtuoso’s Analog Design Environment MediaTek / Cadence	Synopsys / Ansys / Keysight mmWave Reference Design Flow on TSMC N16FFC Synopsys / Ansys / Keysight
11:30 – 12:00	A Unified Approach to 3DIC Power and Thermal Integrity Analysis Through TSMC 3Dblox Architecture and Ansys RedHawk-SC Platform Ansys	Achieving Best Performance-per-Watt at TSMC’s N2 and N3E Hybrid-Row Process Technology Nodes using Fusion Compiler and the Fusion Design Platform Synopsys	Breakthrough platform for AIoT markets Dolphin Design
12:00 – 13:00	Lunch & Ecosystem Pavilion
13:00 – 13:30	SerDes clocking catered to robust noise handling in advanced process technologies for HPC, Datacenter, 5G and AI applications eTopus Technologies / Siemens EDA	An Accurate and Low-Cost Flow for Aging-Aware Static Timing Analysis Synopsys / TSMC	Cadence mmWave Solutions Support TSMC N16 Design Reference Flow Cadence
13:30 – 14:00	Advanced Assembly Verification for TSMC 3DFabric™ Packages Broadcom / Siemens EDA	Analog Design Migration Flow from TSMC N5/N4 to N3E with Synopsys Case Study Synopsys	Analysis of Design Timing Effects of Threshold Voltage Mistracking between Cells Synopsys
14:00 – 14:30	Simplifying Multi-chiplet design with a unified 3D-IC platform solution for 3Dblox technology Cadence	Low power high density design implementation for AI chip Hailo Technologies / Siemens EDA	RISC-V is delivering performance and power efficiency from Embedded to Automotive to HPC SiFive
14:30 – 15:00	Advanced Auto-Routing for TSMC^® InFO™ Technologies Cadence	Reliable compute – taming the soft errors Arm	TSMC, Microsoft Azure and Siemens EDA Collaboration – Enabling Your Jump to N3E using the Cloud and Calibre nmDRC Siemens EDA / Microsoft
15:00 – 15:30	Coffee Break & Ecosystem Pavilion
15:30 – 16:00	3D System Integration and Advanced Packaging for next-generation multi-die system design using Synopsys 3DIC Compiler with TSMC 3DBlox and 3DFabric Synopsys	Self-testing PLLs for advanced SoCs Silicon Creations	HPC & Networking Trends Influencing High-Speed SerDes Requirements Synopsys
16:00 – 16:30	TSMC 3DBlox Simplifies Calibre Verification and Analysis Siemens EDA	Cadence Cerebrus AI driven design optimization pushes PPA on TSMC 3nm node Cadence	Integration Methodology of High-End SerDes IP into FPGAs based on Early Technology Model Availability Achronix / Alphawave IP
16:30 – 17:00	GUC’s GLink case study: Performance and reliability monitoring for heterogeneous packaging, combining deep data with machine learning algorithms proteanTecs	Kick-off your design success with Automated Migration of Virtuoso Schematics Cadence	Pinless Clocking and Sensing Analog Bits
17:00 – 17:30	Achieve 400W Thermal Envelope for AI-Enabled Data Center SoCs – Challenge Accepted Alchip / Synopsys	Delivering best TSMC 3nm power and performance with Cadence digital full flow Cadence	Understanding UCIe for Multi-Die Systems Leveraging CoWoS and Substrate Packaging Technologies Synopsys
17:30 – 18:30	Networking and Reception

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TSMC (TWSE: 2330, NYSE: TSM) created the semiconductor Dedicated IC Foundry business model when it was founded in 1987. TSMC served about 535 customers and manufactured more than 12,302 products for various applications covering a variety of end markets including smartphones, high performance computing, the Internet of Things (IoT), automotive, and digital consumer electronics.

Annual capacity of the manufacturing facilities managed by TSMC and its subsidiaries exceeded 13 million 12-inch equivalent wafers in 2021. These facilities include four 12-inch wafer GIGAFAB® fabs, four 8-inch wafer fabs, and one 6-inch wafer fab – all in Taiwan – as well as one 12-inch wafer fab at a wholly owned subsidiary, TSMC Nanjing Company Limited, and two 8-inch wafer fabs at wholly owned subsidiaries, WaferTech in the United States and TSMC China Company Limited.

In December 2021, TSMC established a subsidiary, Japan Advanced Semiconductor Manufacturing, Inc. (JASM), in Kumamoto, Japan. JASM will construct and operate a 12-inch wafer, with production targeted to begin by the end of 2024. Meanwhile, the Company continued to execute its plan for an advanced semiconductor fab in Arizona, the United States, with production targeted for 2024. www.tsmc.com

Also Read:

Future Semiconductor Technology Innovations

TSMC 2022 Technology Symposium Review – Advanced Packaging Development

TSMC 2022 Technology Symposium Review – Process Technology Development

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