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Create Beyond the NoC Solutions!

Create Beyond the NoC Solutions!
by Eric Esteve on 03-18-2013 at 9:09 am

The Network On Chip (NoC) concept is recent, about 10 years old, and the first implementation of commercially available NoC IP has happened in 2006. Should we drop the concept so quickly after it has been introduced? In fact, I don’t think so… But we could brain storm and imagine the new functions that could be implemented within or around the NoC, benefiting from the existing NoC architecture. Ever increasing SoC complexity generates needs for new functionalities, like error correction and resiliency to increase data robustness, software observability or cache coherency and distributed virtual memory in multi CPU SoC. The NoC provides a ready to use infrastructure (the physical links where to move data), packet based communication protocol (logical way to transport data), so why not using existing NoC physical and logical architecture and go “Beyond the NoC”: implement various serviced functionalities, opportunistically using the NoC to save real estate, power consumption and design resource?

Let’s have a look at additional SoC features and services, which are not the SoC primary functions, but need to be implemented in order to address SoC requirements, in some cases specific to addressed market segments.

  • Error correction and resiliencyare needed in markets like automotive, medical and industrial

    • If you want to add parity bits, ECC checking and other capabilities to ensure no data corruption, you may add it to the NoC transport protocol
    • Resiliency: Current resilient SoCs duplicate much of the interconnects within the chip to be able to test for errors. Using existing NoC infrastructure (logic and wires), you can implement identical error detection and correction functionalities without having to duplicate the entire NoC, therefor providing the same functionalities but saving real estate (die size) and minimizing power consumption.

  • SoC power management: in large SoC, designed in the latest technology nodes (28 nm and below), the power consumption is almost taking precedence on pure performance. Today’s SoC designs addressing various mobile electronic application have to provide multiple high performance features (Video, Imaging, Voice, Data broadband) within the smallest possible power budget, so battery operated system can run during days instead of hours. Implementing the power management techniques is still a “hand made” design process, and you need a specific team to do it.
  • I found a very interesting article, presented a DAC 2009, titled “NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs”. In fact, in this article, the authors have created a NoC to connect all the power islands, supporting power gating of the islands, which sounds like a good idea: they have automated the tasks previously made by hand. It could be an ever better idea if the SoC architect could use the existing NoC as a foundation for power management purpose… Authors have used this algorithm:

  • Security: Every company has their own proprietary on-chip security schemes, including secure boot, data encrypt/decrypt (PKI), etc. It is already possible to create special “placeholders” within the NoC, where designers can insert their own proprietary security IP and logic. This allows the designer to retain 100% control of their security IP, we know how sensible such a service can be today. But this topic is also becoming a real concern for the 3[SUP]rd[/SUP] party IP providers, and they also could take benefit of such “placeholders” and have their security IP being inserted as well.

  • Software observability for debug: the TTM requirements are pushing for more efficient H/W and S/W co-development, and faster S/W integration and debug. Various S/W tracing mechanisms are already being used, like for example CoreSight On Chip Trace and Debug Architecture from ARM, but the NoC can offer additional probing capabilities. By definition of a Network on Chip, the NoC allow accessing every important block within the SoC, not only the CPU related blocks.

We have proposed a few examples, where the NoC can be a foundation for additional SoC features and services, and I am sure that creative designers will come up with other ideas. Architects first implement a NoC to take benefit of the communication capabilities, and to optimize their SoC architecture, as we have discussed here in Semiwiki. Once this NoC infrastructure is on chip, it could be possible to go “Beyond the NoC” and implement additional feature or service. Because you then use already “amortized” logic gates and wires, using NoC as a foundation to introduce new features, that you would introduce anyway (think On-chip Power Management for example), will allow to save Silicon, but not only! You would also save resource and creative energy, and finally launch faster a better SoC on the market. Beyond the NoC is a concept: either Arteris, either creative 3[SUP]rd[/SUP] party start-up or even SoC architect, could develop new features or services mapped to the existing NoC infrastructure and proven communication scheme, to create denser and smarter SoC.

By Eric Esteve from IPNEST