An Update on IP Lifecycle Management (IPLM)

An Update on IP Lifecycle Management (IPLM)
by Bernard Murphy on 06-03-2026 at 6:00 am

IP Lifecycle Management

IPLM is not always prominent, nevertheless it is a very necessary aspect of semiconductor (and systems) design. Modern designs build on a wide range of IPs and subsystems, each evolving through multiple variants and versions, each with different PPA characteristics and recommended use-cases, many from different suppliers… Read More


SRAM compilers targeting automotive SoCs on advanced nodes

SRAM compilers targeting automotive SoCs on advanced nodes
by Don Dingee on 05-27-2026 at 6:00 am

Automotive versus consumer grade reliability

Processor IP garners the most attention in SoC design, but it’s not the only IP category begging for smart choices. Every processor core needs to be fed with data; however, frequent off-chip DRAM access incurs a large clock-cycle penalty each time. Architects now want SRAM blocks distributed throughout an SoC, putting data close… Read More


Power-SOI: The Reliability Engine Behind Functional Safety ICs

Power-SOI: The Reliability Engine Behind Functional Safety ICs
by Daniel Nenni on 05-25-2026 at 6:00 am

Power SOI The Reliability Engine Behind Functional Safety ICs

Power-SOI technology is rapidly emerging as a foundational platform for next-generation functional safety integrated circuits used in autonomous vehicles, industrial automation, humanoid robotics, and other mission-critical systems. The growing convergence of high-voltage power management and low-voltage digital… Read More


Configurable xSPI memory controller IP core is FuSa-ready

Configurable xSPI memory controller IP core is FuSa-ready
by Don Dingee on 05-13-2026 at 10:00 am

xSPI-MC block diagram

SPI, invented some four decades ago, is so successful as a low-pin-count interface for microcontrollers and processor cores that it spurred memory makers to incorporate both the physical signaling interface and advanced memory command protocols into serial flash and serial pseudo-SRAM (PSRAM) devices. Those protocols, … Read More


Speculation: Silicon’s Most Expensive Compulsion

Speculation: Silicon’s Most Expensive Compulsion
by Admin on 04-16-2026 at 10:00 am

SemiWiki Art

How Time-Based Scheduling
Reclaims Silicon Wasted by Speculative Execution

By: Dr. Thang Tran, Founder and CTO, Simplex Micro

I have spent my career designing processor architectures, and I have reached an uncomfortable conclusion: a substantial fraction of the silicon area and power in modern high-performance processors… Read More


Effective Defense Against Hacks at the Edge

Effective Defense Against Hacks at the Edge
by Bernard Murphy on 04-15-2026 at 6:00 am

Hacker attacking edge devices

IoT permeates every aspect of our lives, in payment systems, access authorization, vehicles, utilities, factories, hospitals, and in so many other fields. Which makes these systems attractive targets for hacking and social disruption while also challenging to protect given the highly constrained resources that many such… Read More


Renesas Scalable Automotive SoC Design Using Arteris NoC

Renesas Scalable Automotive SoC Design Using Arteris NoC
by Daniel Nenni on 04-14-2026 at 8:00 am

Arteris IP Renesas ADAS SoC

The increasing complexity of advanced driver assistance systems (ADAS) and automated driving architectures has driven a transition from traditional bus-based interconnects to scalable Network-on-Chip (NoC) fabrics. Renesas’ next-generation R-Car automotive SoC platforms adopt Arteris FlexNoC interconnect intellectual… Read More


CEO Interview with Steve Kim of Chips&Media

CEO Interview with Steve Kim of Chips&Media
by Daniel Nenni on 04-10-2026 at 6:00 am

C&M CEO Steve 2

I’m Steve Kim, the CEO of Chips&Media. I’ve been immersed in the multimedia imaging industry for approximately two decades. Prior to joining Chips&Media, I spent over five years working within handset manufacturing companies. Following more than ten years here at Chips&Media in roles spanning Marketing, Sales,… Read More


NXP Expands Arteris NoC Deployment to Scale Edge AI Architectures

NXP Expands Arteris NoC Deployment to Scale Edge AI Architectures
by Daniel Nenni on 04-09-2026 at 8:00 am

NXP announcement v4b 021026 FINAL

As edge AI systems become more centralized and compute-dense, on-chip data movement is increasingly the architectural bottleneck. NXP’s expanded deployment of Arteris network-on-chip (NoC) and cache-coherent interconnect IP highlights a broader industry trend: interconnect architecture is now a first-order design … Read More


From SoC to System-in-Package: Transforming Automotive Compute with Multi-Die Integration

From SoC to System-in-Package: Transforming Automotive Compute with Multi-Die Integration
by Daniel Nenni on 04-08-2026 at 10:00 am

Types of Mutli Deisgn Packaging Synsopsys

Modern automotive electronics are undergoing a rapid transformation driven by increasing compute demands, functional safety requirements, and the shift toward scalable semiconductor architectures. One of the most significant technological developments enabling this transformation is the adoption of multi-die system… Read More