Abstract:
Stacked dynamic random access memory (DRAM) technology has garnered considerable attention as a means to continue the relentless pursuit of scaling. In this context, we have developed a five-layer horizontal cell with vertical word line (WL) and pillar capacitor to realize a stacked DRAM architecture. This design boasts an excellent combination of high on-state and off-state current ratio ( Ion / Ioff) of ~1E8, a steep subthreshold slope (SS) of ~93 mV/dec and a moderate threshold voltage ( Vt) of 0.76 V. A novel process integration scheme incorporating boron silicate glass (BSG)/phosphorus silicate glass (PSG) capping doping, double gate formation, channel thickness optimization, and device electrical engineering considerations are presented and discussed. Moreover, we have also explored the feasibility of fabricating a 64-layer structure through the development of critical unit processes. This study suggests a promising approach using multilayer horizontal cells (MHCs) to further advance the scaling of DRAM technology.
My take: The unit cell is 0.280 um x 0.435 um (a generously wide footprint), which gives 525 Mb/mm2 in 64 layers. The CMOS is expected to be under or bonded over the array, not adding extra area outside. Since 1c still puts periphery outside the array, this 64-layer gets to 1c range (<600 Mb/mm2).
Stacked dynamic random access memory (DRAM) technology has garnered considerable attention as a means to continue the relentless pursuit of scaling. In this context, we have developed a five-layer horizontal cell with vertical word line (WL) and pillar capacitor to realize a stacked DRAM architecture. This design boasts an excellent combination of high on-state and off-state current ratio ( Ion / Ioff) of ~1E8, a steep subthreshold slope (SS) of ~93 mV/dec and a moderate threshold voltage ( Vt) of 0.76 V. A novel process integration scheme incorporating boron silicate glass (BSG)/phosphorus silicate glass (PSG) capping doping, double gate formation, channel thickness optimization, and device electrical engineering considerations are presented and discussed. Moreover, we have also explored the feasibility of fabricating a 64-layer structure through the development of critical unit processes. This study suggests a promising approach using multilayer horizontal cells (MHCs) to further advance the scaling of DRAM technology.
My take: The unit cell is 0.280 um x 0.435 um (a generously wide footprint), which gives 525 Mb/mm2 in 64 layers. The CMOS is expected to be under or bonded over the array, not adding extra area outside. Since 1c still puts periphery outside the array, this 64-layer gets to 1c range (<600 Mb/mm2).