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Time-saving modules expand Prototype Ready family

Time-saving modules expand Prototype Ready family
by Don Dingee on 07-13-2016 at 4:00 pm

A big advantage of FPGA-based prototyping is the ability to run real-world I/O at-speed, significantly faster and more accurately than hardware emulation systems typically requiring a protocol adapter. Dealing with real-world I/O means more thorough verification of SoC integration, and the opportunity to optimize systems pre-silicon.

Most FPGA-based prototyping platforms have some type of daughterboard expansion strategy, where either the vendor or their customers can add I/O physical hardware quickly and reliably. As more prototyping projects are engaged, vendors get a better feel for what types of I/O their customers need, and often design off-the-shelf I/O modules with supporting software for sale.

Such is the case with S2C, having built their I/O library to over 90 pre-engineered Prototype Ready interface cards for their Prodigy platform. In the latest release this week, S2C added eight new modules to the Prototype Ready family. Their choices of functions to add were particularly interesting, indicating just how broadly FPGA-based prototyping is being adopted.

First are two networking-related interfaces. A popular form factor in data center and telecom applications is the SFP (small form factor pluggable) transceiver; one of the new modules allows a standard SFP to plug in. Another module provides a 3 channel GMII PHY interface for Ethernet applications.

Next is storage, with a SATA3 module for quickly connecting HDDs or SSDs. It provides two SATA hosts each with speeds up to 6 GB/sec. Quickly and simply adding storage to a prototype, especially something like an IoT gateway with localized real-time analytics, is a big plus.

Then there is a Swiss army module, officially called the Processor Peripheral Module providing boot flash in NAND, NOR, and SPI formats, and JTAG and ARM ETM debugger ports. Customers could certainly design something for this, but having an off-the-shelf solution for basic required functions speeds up the time to set up a prototype.

Three more modules handle adaption of popular expansion formats into the Prodigy connector. Two modules focus on the industry-standard FMC form factor. There’s nothing magic to the FMC specification; it standardizes a connector style, pinout, and module size. (Near-useless trivia: yours truly designed the FMC logo while working with VITA.) A Prodigy to FMC-LPC module converts one Prodigy I/O connector to one FMC-LPC I/O connector. A Prodigy to FMC-HPC module converts two Prodigy I/O connectors to one FMC-HPC and one FMC-LPC I/O connector. In a nod to the popularity of Synposys HAPS, the third adapter module converts a Prodigy I/O connector to three HT3 (HAPSTrak 3) I/O connectors. This vastly expands the range of available daughtercard I/O hardware for Prodigy, and facilitates interconnect between Prodigy and HAPS platforms.

Finally, there is a simple but often overlooked module. Daughtercards present a unique problem in design – they are designed to be extremely low profile, but that requires componentry to fit between the PCB and the height of the daughterboard connector. When just trying to prototype something quickly, this height constraint can bog design teams down by restricting what parts can be chosen. A spacer module adds 17.5mm to the height between the Prodigy socket and the Prodigy mezzanine connector, relaxing the height constraint and allowing better choice of components and chip packages. Again, these are time savers for customers.

With more on these S2C prototyping I/O modules, the full press release:

FPGA Prototyping Becomes Even More Precise with Latest Additions to S2C’s World-Class Prodigy Prototype Ready Interface Library

These modules may seem trivial, but any design team who has ever stared at a relatively expensive high-performance processor or FPGA board waiting for a simple cable, power supply, or I/O daughtercard should appreciate the effort S2C is putting into the Prototype Ready family. The choice of available I/O widens a gap between prototyping and emulation and gets customers working on their actual problems in SoC verification faster.