Apple’s iPhone 17 Series 5G mmWave Antenna Module Revealed to be Powered by Soitec FD-SOI SubstratesRecent independent teardown and technical analyses have confirmed…Read More
Advancing Automotive Memory: Development of an 8nm 128Mb Embedded STT-MRAM with Sub-ppm Reliability IEDM 2025 Papers MRAM…Read More
AI Drives Strong Semiconductor Market in 2025-2026The global semiconductor market in 2025 was $792…Read More
How Customized Foundation IP Is Redefining Power Efficiency and Semiconductor ROIAs computing expands from data centers to edge…Read More
Akeana Partners with Axiomise for Formal Verification of Its Super-Scalar RISC-V CoresAkeana Inc. announced a key milestone in the…Read More
One of the truisms of today’s disaggregated semiconductor design and manufacturing model is counter-intuitive to the do-it-yourself focus that is at the heart of every engineer. And yet, time and time again, success rewards those who understand that with today’s ever increasing complexity, it is difficult, if… Read More
Remember the processor-memory gap— a situation where the processor is forced to stall while waiting for a memory operation to complete? This was largely a result of the high latency required for off chip memory accesses. Haven’t we solved that problem now with SoCs? SoCs are typically architected with their processors … Read More
Next week it is Semicon West in the Moscone Center from Tuesday to Thursday, July 10-12th. Cadence will be on a panel session during a session entitled The 2.5D and 3D packaging landscape for 2015 and beyond. This starts with 3 short keynotes:
When I first came to the US, one project that we had going on at VLSI Technology was an ASIC design being done by a French company called Telic. The chip would go into something called “Minitel” which the France Telecom (actually still the PTT since post and telecomunications had not yet been separated) planned to supply… Read More
In my circuit design past I did DRAM work at Intel, so I was interested in learning more about Novocell Semiconductor and their design of One Time Programmable (OTP) IP. Walter Novosell is the President/CTO of Novocell and talked with me by phone on Thursday.… Read More
At DAC in June I didn’t get a chance to visit ClioSoft for a product update so instead I read their white paper this week, “The Power of Visual Diff for Schematics & Layouts“. My background is transistor-level IC design so anything with schematics is familiar and interesting.
The Challenge
Hand-crafted … Read More
SEMICON West is coming up this July 10-12 at the Moscone Center in San Francisco. It covers a broad swath of the microelectronics supply chain, but I was particularly interested in the test sessions. Here are two that I recommend.
“The Value of Test for Semiconductor Yield Learning” on Tuesday, July 10, at 1:30p. The… Read More
If we look at SoC design evolution, we have certainly successfully passed several steps: from transistor by transistor IC design using Calma up to design methodology based on the integration of 500K + gates IP like PCIe gen-3 Controller, one out of several dozens of IP integrated in today’ SoC for Set-Top-Box or Wireless Application… Read More
For those of you who didn’t get to DAC you can catch up on low power issues with Apache’s series of low-power webinars taking place late in July. All webinars are at 11am Pacific Time. Full details and registration on the Apache website here.… Read More
I wasn’t going to write about the cell phone business again for some time. After all, this is a site about semiconductor and EDA primarily. But the cell-phone business in all its facets is a huge semiconductor consumer and continues to grow fast (despite my morbid focus on those companies that do anything but).
But Research… Read More
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A Detailed History of Samsung Semiconductor