Balancing the Demands of OTP for Advanced Nodes with Synopsys IPOne-time programmable (OTP) non-volatile memory has been around…Read More
Synopsys Webinar: The Importance of Security in Multi-Die Designs - Navigating the Complex LandscapeIn today's rapidly evolving digital landscape, the security…Read More
Keysom and Chipflow discuss the Future of RISC-V in Automotive: Progress, Challenges, and What’s Nextby, Tomi Rantakari CEO ChipFlow & Luca Testa…Read More
Synopsys Executive Forum: Driving Silicon and Systems Engineering InnovationThe annual SNUG (Synopsys Users Group) conference, now…Read More
Cadence this morning announced that it has acquired Azuro. Azuro has become a leader in building the clock trees for high performance SoCs. A good rule of thumb is that the clock consumes 30% of the power in an SoC so optimizing it is really important. Terms were not disclosed.
The clock trees involve clock gating which can reduce clock… Read More
At DAC I talked with Mike Dimelow of ARM about the latest upcoming revision to the AMBA bus standards, AMBA 4. The standard gets an upgrade about every 5 years. The original ARM in 1992 ran at 10MIPS with a 20MHz clock. The first AMBA bus was a standard way to link the processor to memories (through the ARM system bus ASB) and to peripherals… Read More
Design for test (DFT) imposes various restrictions on the design so that the test automation tools (automatic test pattern approaches such as scan, as well as built-in self-test approaches) will subsequently be able to generate the test program. For example, different test approaches impose constraints on clock generation… Read More
Intel’s new Tri-Gate technology is causing quite a stir on the stock chat groups. Some have even said if Intel uses its Tri-Gate technology on only Intel processors ARM will be in deep deep trouble. These guys are “Intel Longs” of course and they are battling “Intel Shorts” with cut and paste news clips.
“ARM is in trouble & this… Read More
At DAC 2011 in San Diego, Apache gave many product presentations. Of course not everyone could make DAC or could make all the presentations in which they were interested. So from mid-July until mid-August these presentations will be given as webinars. Details, and links for registration, are here on the Apache website.
The seminars… Read More
During last week-end, I had the good surprise to meet with one of my oldest friend, Eric, who remind me the old time, when we were working together as ASIC designers for… a Supercomputer project.
In France, in a French company (Thomson CSF) active in the military segment and being able to spend which was at that time a fortune ($25M) … Read More
Interesting notes from my most recent Taiwan trip: Taiwan unemployment is at a record low. Scooters once again fill the streets of Hsinchu! TSMC will be passing out record bonuses to a record amount of people. TSMC Fab expansions are ahead of schedule. The new Fab 15 in Taichung went up amazingly fast with equipment moving in later… Read More
In my rush on Wednesday at DAC I had almost over-looked the last two companies I talked with: Invarian and AnaGlobe. These last two I had hand-written notes on paper, so I just got to the bottom of my inbox tonight to write up the final trip reports.
Invarian
Jens Andersen and Vladimir Schellbach gave me an overview of tools that perform… Read More
We all knew that Apache had filed for an IPO earlier and were just waiting for the timing and price to be revealed. Rumors have been circulating about an acquisition and today we know that the rumors were true asAnsys paid $310 million in cash for Apache.
Ansys stock has surged some 35% over the past twelve months:
Products
This acquisition… Read More
The recent announcement from Cadence, officially launching the PCI Express 3.0 Controller IP, as well as the associated Verification IP (VIP), made of Compliance Management System (CMS) which provides interactive, graphical analysis of coverage results, and PureSuite which provides the PCIe associated test cases, clearly… Read More
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Achieving Seamless 1.6 Tbps Interoperability for High BW HPC AI/ML SoCs: A Technical Webinar with Samtec and Synopsys