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Semiconductor Industry Damage Assessment (Disaster in Japan)

Semiconductor Industry Damage Assessment (Disaster in Japan)
by admin on 03-19-2011 at 5:19 am

The earthquake and subsequent tsunami that devastated Japan on March 11[SUP]th[/SUP], 2011 will have far reaching ramifications around the world for years to come. People have asked me how this disaster will affect the semiconductor industry so I will try and summarize it in this blog.

First the foundries:

According to TSMC: Read More


How much IP & reuse in this SoC?

How much IP & reuse in this SoC?
by Eric Esteve on 03-17-2011 at 10:12 am

According with the survey from GSA-Wharton design IP blocks reuse in a new IC product is 44% in average. Looking at the latest Wireless platform from TI, OMAP5, we have listed the blocks which have been (or will be) reused, coming from internal (or external) IP sourcing. For a license cost evaluation of -at least- $10M!

For those whoRead More


Apache files S-1

Apache files S-1
by Paul McLellan on 03-14-2011 at 3:50 pm

Apache Design Solutions today filed their S-1 with the SEC in preparation for its initial public offering (IPO). This is a big deal since there hasn’t been an IPO of an EDA company for may years (Magma was the last 10 years ago). As a private company they have not had to reveal their financials until now.

It turns out that they did… Read More


Checking AMS design rules instantly

Checking AMS design rules instantly
by Paul McLellan on 03-13-2011 at 5:25 pm

With each process generation, the design rules get more and more complex. One datapoint: there are twice as many checks at 28nm as there are at 90nm. In fact, the complexity of the rules is outpacing the ability to describe them using the simplified approaches used in the DRCs built-into layout editors or formats like LEF.

Worse still,… Read More


Moore’s Law and Semiconductor Design and Manufacturing

Moore’s Law and Semiconductor Design and Manufacturing
by Daniel Nenni on 03-12-2011 at 4:51 am

The semiconductor design and manufacturing challenges at 40nm and 28nm are a direct result ofMoore’s Law, the climbing transistor count and shrinking geometries. It’s a process AND design issue and the interaction is at the transistor level. Transistors may be shrinking, but atoms aren’t. So now it actually matters when even… Read More


Getting Real Time Calibre DRC Results

Getting Real Time Calibre DRC Results
by Daniel Payne on 03-10-2011 at 10:00 am

Last week I met with Joseph Davis, Ph.D. at Mentor Graphics in Wilsonville, Oregon to learn about a new product designed for full-custom IC layout designers to improve productivity.

The traditional flow for full-custom IC layout designers has been nearly unchanged for decades:

  • Read a schematic or use Schematic Driven Layout
Read More

Semiconductor IP would be nothing without VIP…

Semiconductor IP would be nothing without VIP…
by Eric Esteve on 03-10-2011 at 6:35 am

…but what is the weight of the Verification IP market?

If the IP market is a niche market (see: **) with revenue of about 1% of the overall semiconductor business, how could we qualify the VIP market? Ultra-niche market? But the verification of the IP integrated into the SoC is an essential piece of the engineering puzzle when you areRead More


Apple Creates Semiconductor Opportunities . . .

Apple Creates Semiconductor Opportunities . . .
by Steve Moran on 03-09-2011 at 7:22 pm

There has been a lot of press this past week surrounding the release of iPad2. While it has some significant improvements, they are, for the most part, incremental. In my view the lack of flash, a USB port and a memory card slot continue to be huge deficits. Until this past week my reservations about the iPad have been mostly theoretical,Read More


TSMC 2011 Technology Symposium Theme Explained

TSMC 2011 Technology Symposium Theme Explained
by Daniel Nenni on 03-09-2011 at 6:49 pm

The 17[SUP]th[/SUP] Annual TSMC Technology Symposium will be held in San Jose California on April 5[SUP]th[/SUP], 2011. Dr. Morris Chang will again be the keynote speaker. The theme this year is “Trusted Technology and Capacity Provider”and I think it’s important to not only hear what people are saying but also understand why… Read More


Essential signal data and Siloti

Essential signal data and Siloti
by Paul McLellan on 03-05-2011 at 3:24 pm

One of the challenges with verifying today’s large chips is deciding which signals to record during simulation so that you can work out the root cause when you detect something anomalous in the results. If you record too few signals, then you risk having to re-run the entire simulation when you omitted to record a signal that… Read More