If I had to describe CES in one word it would be exhausting. There were 3,000+ vendors, 150,000+ people, lines for everything, but 100% pure excitement. Even my beautiful wife was intrigued by the technology that shapes our lives. The smart toaster was of great interest to her since she says I time my toast with the smoke alarm. The … Read More





ESD Check Methodology
In Pune at the start of the month, Norman Chang, Ting-Sheng Ku, Jai Pollayil of Apache/Ansys and NVIDIA presented and ESD check methodologywith Fast Full-chip Static and Macro-level Dynamic Solutions . ESD stands for Elecro-Static Discharge and is basically injecting very high static voltages (think how your hand gets charged… Read More
The First 14nm FinFET Wafer Sighting!
Incredibly exciting! Even my beautiful wife was impressed by the rainbow of colors it reflected. From left to right: 28nm, 20nm, and 14nm wafers. The 20nm and 14nm wafers are from the GLOBALFOUNDRIES NY fab, made in the USA! GF also announced another $3-4B CAPEX for 2013 to increase capacity of all three of their 300mm fabs (Singapore,… Read More
Predictions are hard, especially about the future
I was asked to make some predictions about the EDA, semiconductor and electronic systems markets for 2013. I decided that it would be more fun to make some plausible predictions, some of which will be right, rather than go for anodyne predictions (“Cadence will acquire a couple of startups”) which are uninformative,… Read More
A Brief History of Synopsys DesignWare ® IP
Let’s play word association. I say “EDA”, you immediately think “Synopsys”. I say “IP” and although 15 years ago you may not, today, you think “Synopsys”. For nearly two decades, Synopsys has grown its IP business through both organic development and acquisition, with a clear focus on enabling designers to meet their time-to-market… Read More
TSMC Apple Rumors Debunked!
Disclaimer: I’m a blogger and by definition I share my observations, opinions, and experiences. Journalists and Analysts on the other hand are held to a much higher legal standard which is why they cite undisclosed sources and use double speak to shield themselves legally. Why trust a SemiWiki blogger over a Journalist or an Analyst?… Read More
Reducing Dynamic and Static Power in Memories
Sequential approaches to power reduction work well on logic implemented using standard cells. But part of every SoC, sometimes a very large part, is taken up with embedded memories for which alternative approaches are required. Not only do these memories occupy up to half of the area they also account for as much as 75% of the power… Read More
Global Design Closure
Satish Soman, chief solutions architect at Atrenta, was invited to give a presentation on Global Design Closure at the VLSI India conference in Pune at the start of this month. He talked about the need to close the gap between the typical SoC development methodology and what happens in reality.
SoCs are really put together in two … Read More
IC Design at Analog Bits
This morning I spoke with Mahesh Tirupattur, Executive VP of Analog Bits about IC design challenges and using EDA tools to create high performance, mixed-signal semiconductor IP.
Oasys RealTime Explorer
The current methodology in design in most companies, and certainly many of the biggest, is that front end RTL design is done by one team with a limited set of front-end design tools. This is then eventually passed off to the physical design team who run all the scripts, do the “real” synthesis, place & route and timing… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot