Reimagining 3D IC Design: From Architecture to SignoffBy Keith Felton, Andras Vass-Varnai and Todd Burkholder,…Read More
GSA Honors Sanjay Mehrotra as Memory Takes Center Stage in ComputingThe Global Semiconductor Alliance will present Micron Technology…Read More
NIST Sets a Clearer Course for the Post-Quantum Security TransitionNIST’s report, Transition to Post-Quantum Cryptography Standards, gives…Read More
CTO Interview with Ed Plowman of Imagination TechnologiesEd Plowman is Chief Technology Officer at Imagination…Read More
Ceva’s next NeuPro generation opens new possibilities across AICeva is broadening the possibilities for AI silicon…Read More
As the PC Era took shape, Tom Peters predicted the shift away from “where all the cars are parked”. He foresaw that large, established companies would no longer be the economic engine, or the dominant force in innovation. Smaller firms, even individuals, would rise to prominence in a new, technologically-driven economy.
That … Read More
One of the most important and underrated tasks in a semiconductor company is creating the cost model. This is needed in order to be able to price products, and is especially acute in an ASIC or foundry business where there is no sense of a market price because the customer and not the manufacturer owns the intellectual property and … Read More
I will have the privilege to give an “IP Outlook” presentation during next Cadence event in Europe, CDN-Live to be held in Munich the 19[SUP]th[/SUP] to 21[SUP]st[/SUP] of May. I had a look at the agenda, and the conference will be pretty busy, especially on Tuesday, as there will be more than fifty presentations, starting at 10:30… Read More
DAC is coming up in a month (OMG less than 4 weeks and we are so not ready I hear a hundred marketing people cry out). That gives you four weeks (and a couple of days) to tell Mentor what you do in your spare time that you are passionate about (spare time, I hear a hundred engineers cry out, what is that?) and you could win $300.
For DAC, Mentor… Read More
The COO of ST Microelectronics, Jean-Marc Chery announced that they have signed a new foundry agreement for FD-SOI. What he actually said doesn’t reveal who the foundry in question is:“We have just signed a strategic agreement with a top-tier foundry for 28nm FD-SOI technology. This agreement expands the ecosystem, assures… Read More
I will say that as popular as DO-254 and the like is, I am not the fella for that. It can take the simplest of designs into a realm of test and verification like you have never seen before. Yes, when I am flying I happen to be a big fan of this rigorous testing but you will not find me doing that job anytime soon. While the topic is very dry, it … Read More
DACis just 33 days away and who wouldn’t want a cool GoPro camerato play with? Your manager will certainly want you to first check out what’s new at DAC if your job involves getting to RTL signoff on time and within budget. The creative folks at Atrenta have figured out how to attract us with the offer of winning a GoPro camera,… Read More
ANSYS acquired Apache Design Automation back in June 2011and three years later the name “Apache” is being subdued in favor of using just ANSYS. One thing that I noticed right away was a DACfocus on having actual ANSYS customers talk about their hands-on experience using the EDA tools. The following seven customers… Read More
The Electronic Design Process Symposium is an annual workshop run by the IEEE Computer Society of Silicon Valley and the IEEE Council on Electronic Design Automation. I presented there because it’s devoid of product marketing pitches, and is two days of discussion on technical and process issues in SoC design. My slides are here:… Read More
The big three in EDA are well-know for offering AMS and RF IC design flows, but today you also have alternative EDA vendors available that have capable tools, yet are lessor known. This blog will present an overview of the AMS and RF IC design flowoffered by Silvaco, an EDA company with a strong history in TCAD tools like Utmost IV for… Read More
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The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival