TSMC Describes Technology Innovation Beyond A14The inaugural event for the 2025 TSMC Technology…Read More
SNUG 2025: A Watershed Moment for EDA - Part 2At this year’s SNUG (Synopsys Users Group) conference,…Read More
Feeding the Beast: The Real Cost of Speculative Execution in AI Data CentersFor decades, speculative execution was a brilliant solution…Read More
LLMs Raise Game in Assertion Gen. Innovation in VerificationLLMs are already simplifying assertion generation but still…Read More
Automotive Functional Safety (FuSa) ChallengesModern vehicles have become quite sophisticated, like a…Read More
Let’s play word association. I say “EDA”, you immediately think “Synopsys”. I say “IP” and although 15 years ago you may not, today, you think “Synopsys”. For nearly two decades, Synopsys has grown its IP business through both organic development and acquisition, with a clear focus on enabling designers to meet their time-to-market… Read More
Disclaimer: I’m a blogger and by definition I share my observations, opinions, and experiences. Journalists and Analysts on the other hand are held to a much higher legal standard which is why they cite undisclosed sources and use double speak to shield themselves legally. Why trust a SemiWiki blogger over a Journalist or an Analyst?… Read More
Sequential approaches to power reduction work well on logic implemented using standard cells. But part of every SoC, sometimes a very large part, is taken up with embedded memories for which alternative approaches are required. Not only do these memories occupy up to half of the area they also account for as much as 75% of the power… Read More
Satish Soman, chief solutions architect at Atrenta, was invited to give a presentation on Global Design Closure at the VLSI India conference in Pune at the start of this month. He talked about the need to close the gap between the typical SoC development methodology and what happens in reality.
SoCs are really put together in two … Read More
This morning I spoke with Mahesh Tirupattur, Executive VP of Analog Bits about IC design challenges and using EDA tools to create high performance, mixed-signal semiconductor IP.
The current methodology in design in most companies, and certainly many of the biggest, is that front end RTL design is done by one team with a limited set of front-end design tools. This is then eventually passed off to the physical design team who run all the scripts, do the “real” synthesis, place & route and timing… Read More
Who makes the decision and declare that a specific interface protocol is successful? Not me, as I can only consolidate market share data and some insight information coming from the industry. The end user, when going to a shop (real or virtual) and spend a significant part of his budget to buy an electronic product, selecting among… Read More
Sidense will be exhibiting at the Common Platform Technology Forum in Santa Clara, California on February 5, during which time they will be discussing their one-transistor, one-time programmable (1T-OTP) memory IP products. Based on their patented 1T-Fuse™ bit cell, Sidense antifuse-based 1T-OTP macros offer a secure, reliable,… Read More
“It’s not like we started it,” said Larry. “After all the idea of going Thermonuclear was first broached by Steve to Eric at their outdoor café meeting in Palo Alto way back in 2010. We’re just following by example and as Steve was wont to quote Picasso; “good artist copy, great artist steal” so why not go Thermonuclear with our Android… Read More
Time to pack up for the 2013 Consumer Electronics Show in Las Vegas, I will be driving down with my beautiful wife Shushana because she does not like to fly. The drive takes the better part of a day so we will leave early and see the sunrise over the desert. She is great company, the time will fly by. We will be 2 of the more than 150,000 people… Read More
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Intel’s Path to Technological Leadership: Transforming Foundry Services and Embracing AI