Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICsAn engineering change order, or ECO in the…Read More
The Rise, Fall, and Rebirth of In-Circuit Emulation (Part 1 of 2)Introduction: The Historical Roots of Hardware-Assisted Verification The…Read More
Tessent MemoryBIST Expands to Include NVRAMThe concept of built-in self-test for electronics has…Read More
The Importance of Productizing AI. Everyday ExamplesKeeping up with the furious pace of AI…Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty BetCan cash and IBM collaboration put Japan into…Read More
You may have heard about cell-aware testing. It’s a transistor-level test (ATPG) methodology that is quickly becoming a hot topic. If you are involved in DFT and are looking for better quality and reliability, you should definitely know about cell-aware testing.
And lucky you, on May 16, 2013, you can attend a free seminar on cell-aware… Read More
Global Foundries will be at DAC in booth 1314. There will be 6 pods there demonstrating:
Dassault Systèmes (DS) was created in 1981 when a small team of engineers were spun out of Dassault Aviation. They were developing software to design wind-tunnel models and so reduce the cycle time for wind-tunnel testing, using surface modeling in 3D instead. The company entered into a distribution agreement with IBM that same… Read More
This is an example of what I do during the day. I work with emerging companies on disruptive technologies and help launch them into the fabless semiconductor ecosystem. This product, iDRM, is the result of three years of joint development work amongst three semiconductor foundries and some of their top customers:… Read More
Robert Veltman and Vikash Tyagi of SanDisk Corporation presented at SNUG a few weeks ago on their selection and use of RTDA’s NetworkComputer to manage their workflows.
Like everyone else, SanDisk has a high-performance computing farm (and like everyone else they are coy about how big it is) and lots of licenses for EDA tools,… Read More
This year for the first time the Thursday of DAC is tranining day. So that would be June 6th in Austin, of course. There are four tracks of training focused on SystemC, ARM Cortex and two on SystemVerilog, all areas of increasing use in SoC design, especially in mobile.
Each track of training is divided into two parts, one held from 9am… Read More
I talked to Greg Peterschmidt of Agilent today about their integration of Advanced Design System (ADS) with ClioSoft’s SOS Design Data Management that was announced today. The integrated product is known as SOS viaADS. Greg is the ADS Product Planning Manager.
ADS is the market leader for design of very high frequency stuff… Read More
It was definitely a good idea to go to Munich to listen to the keynote talk from Lip-Bu Tan. Did I learned in direct live the name of the next acquisition from Cadence in 2013, after Tensilica and Cosmic Circuits? Yes and the winner is… Evatronix! And cadence as well as Evatronix is enjoying more than 600 customers worldwide, thanks … Read More
Join us for a free career-building panel at DAC 2013, sponsored by Women in Electronic Design.
· Don’t go it alone! How many times have you heard it?
A lively panel of luminaries discuss how alliances are critical to our success, and cover networking and negotiating skills for achieving personal satisfaction and professional visibility.… Read More
Atrenta are at booth 1847 in the exhibit hall where there will be regular presentations in the “RTL Signoff Theater” and lots of presentations on various aspects of SpyGlass, GenSys and BugScope in their suites. The registration page for the suite sessions is here. Just who is presenting in the RTL Signoff Theater … Read More
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Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet