Static Timing Analysis Signoff - A comprehensive and Robust ApproachBy Zameer Mohammed Once a chip is taped…Read More
Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High-Performance RISC-V CPUsFor decades, high-performance CPU design has been dominated…Read More
Orchestrating IC verification: Harmonize complexity for faster time-to-marketBy Marko Suominen and Slava Zhuchenya of Siemens…Read MoreBasilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status QuoAt Hot Chips 2025, Philippe Sauter of ETH…Read More
It sure has been an interesting experience watching Intel enter the semiconductor foundry business! While I credit Intel for increasing the exposure of the fabless semiconductor ecosystem to the financial markets, the attention from the Intel biased press is a bit overwhelming. The TSMC and ARM bashing is reaching new levels… Read More
On the Tuesday of DAC I moderated a panel session on Hardware Assisted Verification in 10 Years: More Need, More Speed. Although this topic obviously could include FPGA-based prototyping, in fact we spent pretty much the whole time talking about emulation. Gary Smith, on Sunday night, actually set up things by pointing out that… Read More
Custom IC design and layout is becoming more difficult at 20nm and smaller nodes, so the EDA tools have to get smarter and work harder for us in order to maintain productivity with the fewest iterations to reach our specs. Dave Stylesand John Stabenow of Cadence met with me last Monday in Austin at the DAC exhibit area.
John Stabenow… Read More
John Heinleinfrom ARM briefed me at DAC exactly one week ago. I love to use my mobile devices (MacBook Pro, iPad and Samsung Galaxy Note II) every day, and many mobile devices are ARM-powered because of the low power consumption, and pervasive eco-system around the architecture. Apple with the MacBook Pro is still Intel-powered,… Read More
Last year at DAC we didn’t really know the circuit simulation roadmap for Synopsys because of all the EDA company acquisitions, however this year it’s clear to me that:
In a typical analog IC design team, multiple engineers and layout professionals work on cells and libraries. At various points during the design process they will commit changes to their designs into the Design Management (DM) system that manages their files – be it Subversion, Perforce or some other commercial tool.
Using the… Read More
If you have attended DAC in Austin (June 2-5), you probably have missed the first TSMC Technology Symposium. It was held on June 6 in Shanghai. Considering my own experience of a 29 hours trip to come back home (in France), I doubt that it was any possible to leave Austin on June 5 to attend TSMC Technology Symposium in Shanghai on June… Read More
GSA’s next event is the annual Entrepreneurship Conference to be held at the Computer History Museum on July 18th. The event runs from 3pm to 8pm. Attendance is free but you must register here.
The event consists of 5 panel sessions followed by a reception. The full roster of who will be on each panel is not completely finalized… Read More
While eyes remain fixated on the architectural battle between Intel and ARM, a second front is soon about to open up that will determine mobile supremacy for the rest of the decade. Whereas yesterday’s story on the collapse of Wintel and the anointing of Google and Samsung are repeated endlessly, now tables are being set for a significant… Read More
I just don’t understand it? My kids love surprises but I have yet to find management that does, go figure but boy during a review they can really spring them on ya! What surprises me is the absurdness of my title, GPU vs. FPGA. FPGAs are not GPUs and likewise but none the less there is the push to make a fit where nature does not allow. I liken… Read More
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Intel’s Pearl Harbor Moment