Rethinking Phase Jitter: An Algorithmic Approach to Signal IntegrityByline: Richard Shreiner Modern semiconductor architectures are pushing…Read More
Siemens and NVIDIA Accelerate Lithography for Next-Generation AI ChipsSiemens has announced advances in its collaboration with…Read More
TSMC’s AI Expansion Signals a Broader Shift in ComputingTSMC is describing an artificial intelligence boom that…Read More
Terafab's Single Roof: Why Packaging, Not Lithography, Decides High VolumeBy Shaurya Seth Terafab is one of the…Read More
Design the Right Chip: Why Prototyping Has to Be EasyDesign the right chip. Design the chip right.…Read More
Intel (INTC) CEO Brian Krzanich keynoted the Citi Global Technology Conference last week. This was a precursor to the Intel Developer Forum in San Francisco this week. Normally these types of events are scripted dog and pony shows but sometimes interesting information comes out. The first question for example:
What does Intel… Read More
Last week it was a rare opportunity for me to attend a webinar where an SoC design house, a leading IP provider and a leading EDA tool provider joined together to present on how the tool capabilities are being used for advanced mixed-signal simulation of large designs, faster with accuracy. It’s always been a struggle to combine design… Read More
In looking at the SemiWiki analytics, one of the top search terms that brings traffic to our site is ARM, just about anything ARM. In fact, that’s what the next SemiWiki book will be about. Yes, ARM is that interesting. While EDA is also one of our top search terms, EDA+ARM will get the most views, absolutely. And let’s face it, bloggers… Read More
It’s that time of year again! The 4th TSMC Open Innovation Platform Ecosystem Forum is coming up on September 30th. As usual it is in the San Jose conference center. The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and their customers to share real case solutions to today’s design challenges.… Read More
For several weeks I have been trying to put out one blog per day rather than being like London buses where there are none for ages and then three come along at once. Or SFMuni buses for that matter. This week has been more of the same. Well, OK, I skipped labor day because…labor day. All you IC types will be busy eating chips not designing… Read More
With advancement of semiconductor technologies, ever increasing sizes of SoCs bank on higher densities of design rather than giving any leeway towards increasing chip area and package sizes; a phenomenon often overlooked. The result is – larger designs with lesser number of pins bonded out of ever shrinking package sizes;… Read More
Synopsys have been gradually broadening their portfolio of verification IP (VIP). It is 100% native SystemVerilog with native debug using Verdi (that was acquired from SpringSoft last year, now fully integrated into Verification Compiler). It has native performance with VCS. Going forward there are source code test suites.… Read More
We have extensively discussed in Semiwiki about FD-SOI technology, explaining the main advantages (Faster, Cooler, Simpler), sometimes leading to very deep technical discussions, thanks to Semiwiki readers and their posts. I have recently found an article “Samsung & ST Team Up on 28nm FD-SOI”. This article includes many… Read More
I have talked before about how the Internet of Things (IoT) doesn’t require enormous power-hungry SoCs. We all accept, or at least put up with, having to recharge our phones daily. But smart pedometers (or whatever a good name for Fitbit-like products are) had better last for a week or two between charges.
Today, Quicklogic… Read More
No doubt about it, the summer break has ended, it’s time for releasing big announcement, like this one from ARM “Momentum Builds For the Next Generation of ARM Processors”. In fact, the key information is about ARMv8-A market adoption. A total of 27 companies have signed agreements for the company’s ARMv8-A technology as… Read More
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SEMICON West’s Autonomous Fab Vision Needs a Decision-Escalation Design