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SEMICON West: My Top Picks

SEMICON West: My Top Picks
by Paul McLellan on 06-20-2013 at 11:21 am

I will be at Semicon West from 9th to 11th July in Moscone, San Francisco. Of course there are lots of interesting sessions but here are two that I think are especially important to get a good impression of the way things are going in the future from experts. The two most interesting questions about the future are what comes after 14nm,… Read More


What does 3D IC, FinFETs, and EUV have in common?

What does 3D IC, FinFETs, and EUV have in common?
by Daniel Nenni on 06-19-2013 at 6:00 pm


They are three of the top trending terms on SemiWiki and three of the hot topics at this year’s Semicon West:

In its 43rd year, SEMICON West is the flagship annual event for the global microelectronics industry. It is the premier event for the display of new products and technologies for microelectronics design and manufacturing,Read More


Static Low-Power Verification in Mixed-Signal SoC Designs

Static Low-Power Verification in Mixed-Signal SoC Designs
by Daniel Payne on 06-19-2013 at 2:02 pm

IC designer Shubhyant Chaturvediof AMD used EDA tools from Mentor Graphicsand Concept Engineeringto perform static, low-power verification of a mixed-signal SoC design with a combined CPU and GPU. Shubhyant presented a poster session at DAC two weeks ago in Austin, and I wanted to share it with my readers here at SemiWiki.… Read More


A New STA Tool at DAC, No Not Cadence

A New STA Tool at DAC, No Not Cadence
by Daniel Payne on 06-19-2013 at 12:15 pm

The big EDA companies get big attention at DAC, however sometimes the little EDA start-ups like Arcadia Innovationhave a new product that can be overlooked. On Tuesday at DAC I met with Joey Lin, founder of Arcadia Innovation and learned about his new STA (Static Timing Analysis) tool called TimeHawk .… Read More


Deploying 14nm FinFETs in your Next Mobile SoC

Deploying 14nm FinFETs in your Next Mobile SoC
by Daniel Payne on 06-19-2013 at 11:05 am

At DAC in Austin a design company, foundry and EDA vendor teamed up to present their experiences with 14nm FinFETs during a breakfast on Tuesday.

Panelists included:

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Is Your Synchronizer Doing its Job (Part 1)?

Is Your Synchronizer Doing its Job (Part 1)?
by Jerry Cox on 06-18-2013 at 8:30 pm

Recently, I discussed the increasing risk of metastability hazards at nanoscale geometries. These risks are significantly aggravated at low supply voltages and low temperatures and must be addressed during the design cycle of any mission critical application. This time I discuss what it takes to estimate a synchronizer’s … Read More


Derivative Designs Need Tools Too

Derivative Designs Need Tools Too
by Paul McLellan on 06-18-2013 at 11:58 am

Increasingly, SoC designs consist of assembling blocks of pre-designed IP. One special case is the derivative design where not just the IP blocks get re-used but a lot of the assembly itself. For example, in the design below some blocks are added, some blocks are updated, some hierarchy is changed. But the bulk of the design remains… Read More


Increasing Automotive Semiconductor Test Quality

Increasing Automotive Semiconductor Test Quality
by glforte on 06-17-2013 at 4:45 pm

The growing amount of electronics within today’s automobiles is driving very high quality and reliability requirements to a widening range of semiconductor devices. At the same time, traditional fault models are becoming less effective at achieving desired silicon quality levels. Improvements in test solutions are needed… Read More