SILVACO 073125 Webinar 800x100

Semiconductor IP and Correct-by-construction Workspaces

Semiconductor IP and Correct-by-construction Workspaces
by Daniel Payne on 01-21-2014 at 8:00 pm

SoC hardware designers could learn a thing or two from the world of software development, especially when it comes to the topic of managing complexity. Does that mean that hardware designers should literally use a software development environment, and force fit hardware design into file and class-based software methodologies?… Read More


DSPs converging on software defined everything

DSPs converging on software defined everything
by Don Dingee on 01-21-2014 at 5:00 pm

In our fascination where architecture meets the ideas of Fourier, Nyquist, Reed, Shannon, and others, we almost missed the shift – most digital signal processing isn’t happening on a big piece of silicon called a DSP anymore.

It didn’t start out that way. General purpose CPUs, which can do almost anything given enough code, time,… Read More


Happy Birthday GSA

Happy Birthday GSA
by Paul McLellan on 01-21-2014 at 2:57 pm

This year marks the 20th anniversary of GSA and collaboration around the foundry and fabless ecosystem. Originally GSA was FSA, the fabless semiconductor association. There was a semiconductor associations 20 years ago, the SIA, but that was still the “real men have fabs” era and fabless semiconductor companies… Read More


Smart Clock Gating for Meaningful Power Saving

Smart Clock Gating for Meaningful Power Saving
by Pawan Fangaria on 01-21-2014 at 5:30 am

Since power has acquired a prime spot in SoCs catering to smart electronics performing multiple jobs at highest speed; the semiconductor design community is hard pressed to find various avenues to reduce power consumption without affecting functionality and performance. And most of the chips are driven by multiple clocks that… Read More


Digital @ Nano-Scale while Analog Hovers @ 65nm and Above

Digital @ Nano-Scale while Analog Hovers @ 65nm and Above
by Daniel Nenni on 01-20-2014 at 9:00 pm

Who’s going to DesignCon next week? I am, absolutely. Dr. Hermann Eul, Vice President & General Manager, Mobile & Communications Group, Intel Corporation will be keynoting on Tuesday. This one I want to hear! Intel missed mobile at 32nm, 22nm, and 14nm. Lets see what they have planned for 10nm. Something good I hope!… Read More


The Semiconductor Landscape – III

The Semiconductor Landscape – III
by Pawan Fangaria on 01-20-2014 at 12:30 pm

In continuation to my earlier observations and anticipations (landscape1, landscape2) which came up to my expectations, I was further inspired to ponder over the macros of our ever growing semiconductor industry. We may argue the business is stagnating, we may argue that the pace of scaling is slowing, but when I look back at the… Read More


SilabTech Awarded 2013 Best Start-up in India

SilabTech Awarded 2013 Best Start-up in India
by Eric Esteve on 01-20-2014 at 8:32 am

This is obviously great news for SilabTech, and this is the type of news which will change the perception that we (non-Indian) have of the Semiconductor industry in India. About 15-20 years ago, the India Embedded/VLSI industry was perceived as low cost design resource pool, a good place where to implement design center. The hidden… Read More


Intel is NOT Transparent Again!

Intel is NOT Transparent Again!
by Daniel Nenni on 01-19-2014 at 9:00 am

Recent headlines suggest that Intel was not transparent about some of the products they showed at the CES keynote. Intel confirmed on Friday that they used ARM-based chips for some of the products but would not say which ones. When your company’s tag line is “Intel Inside” and you hold up a product during your keynote wouldn’t… Read More


Managing Heat for System Reliability

Managing Heat for System Reliability
by Pawan Fangaria on 01-17-2014 at 8:30 am

In most of the electronic equipments, semiconductor chips are a major source of heat generation. And in semiconductor designs several hardware and software techniques are being used to contain power dissipation; a major cause for heat. However due to multiple functionality being squeezed into small form factors, we continue… Read More


JasperGold COV App, the Swiss Army Knife for Verification

JasperGold COV App, the Swiss Army Knife for Verification
by Paul McLellan on 01-16-2014 at 12:55 am

At the Jasper Users Group meeting in October Rajeev Ranjan presented on the JasperGold COV App which he described as the Swiss army knife for verification. It comes in many sizes and contains many useful tools.

The primary goal of COV is to provide coverage metrics:

  • stimuli coverage: how restrictive is the design behavior under
Read More