Berkeley Design Automation today announced the first silicon-accurate circuit simulation for mega-scale arrays like memories and CMOS image sensors. If this tool lives up to its claims, it is going to be a big deal for FinFET-based circuits, Memory designers are rightly worried about having the accuracy necessary to include… Read More
RTL Signoff Theater
We have talked for years about RTL signoff, the idea that a design could be finalized at the RTL level and then most of the signoff would take place there. Then the design would be passed to a physical implementation team who would not expect to run into any problems (such as routing congestion, missing the power budget or similar problems).… Read More
Transistor, Gate and RTL Debug Update at DAC
Debugging an IC design at the transistor, Gate and RTL levels is often necessary to meet timing requirements and understand analog or digital behavior, yet the process itself can be a tedious one, filled with manual steps, therefore making it an error-prone process. EDA tools have been created to help us graphically debug transistor,… Read More
The never-ending quest to kill metastability
The difficulty of an engineering problem can be gauged by two things:
1) The number of attempts to generate a solution.
2) The degree of hyperbole used to describe the effectiveness of the latest solution.
The problem many folks in the EDA industry are after right now is clock domain crossings (CDCs) and the resulting metastability… Read More
Jasper’s DAC Program
Jasper’s booth is 2346 where you can see demos of the JasperGold Apps and attend seminars on the experiences of ST and Broadcom, and others:
- The Broadcom presentation on making formal an integral part of chip design is Tuesday at 10am.
- The ST presentation on adapting formal methods in ARM subsystems is Monday at 1.30pm and
Barbecue at DAC
I already wrote about Franklin Barbecue, by some rankings the best in the whole country. If you want to go there you must be there early. They start serving at 11am and run out of food around 1pm. Closed on Monday.
But there are other barbecue and similar places near the convention center. Since I’m not an Austin native (we’ll… Read More
Enabling 14nm FinFET Design
There’s never a dull moment in the foundry race to offer FinFET processes that enable leading-edge SoC design. Today I attended a webinar hosted by Samsung and Synopsys on how to enable 14nm FinFET design. The two speakers were Dr. Kuang-Kuo Lin from Samsung and Dr. Henry Sheng from Synopsys.
Dr. Kuang-Kuo Lin, Samsung
Dr.… Read More
Calypto AMD Renesas and #50DAC
This year for DAC, Calypto has assembled an impressive lineup of customer presentation, suite sessions and Designer Tracks. To start with customer presentation, Steve Kommrusch, Fellow Design Engineer from AMD will be giving a talk in the Calypto Suite on AMD’s methodology for low power and will show how AMD was able to get further… Read More
AMS Design, Layout and Verification @ #50DAC
Competition in EDA is absolutely necessary in order for the fabless semiconductor ecosystem to thrive. AMS tools with a low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership. That is why Tanner EDA has shipped over 33,000 licenses of … Read More
IROC Technologies CEO on Semiconductor Reliability
One of the best things about being part of SemiWiki is the exposure to new technologies and the people behind them. SemiWiki now works with more than 35 companies and I get to spend time with each and every one of them. Much like I do, IROC Technologies works closely with the foundries and the top semiconductor companies so it was a pleasure… Read More
Weebit Nano Brings ReRAM Benefits to the Automotive Market