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ASMC 2015 Preview

ASMC 2015 Preview
by Scotten Jones on 05-01-2015 at 7:00 am

From May 3[SUP]rd[/SUP] to May 6[SUP]th[/SUP] the 26[SUP]th[/SUP] annual Advanced Semiconductor Manufacturing Conference (ASMC) will be held in Saratoga Springs, New York.

The ASMC offers a unique view of challenges to the semiconductor industry focusing on things like defect reduction, metrology and fab operations. In… Read More


Can You Really Automate Analog IC Layout?

Can You Really Automate Analog IC Layout?
by Daniel Payne on 04-30-2015 at 7:00 pm

Digital IC design has been largely automated with high-level languages, RTL coding, logic synthesis, and automated place and route tools. What about analog IC layout automation, is it possible? A few EDA companies think that it is possible and even practical. In recent memory there were two companies really focused on analog … Read More


Extending Moore in Silicon

Extending Moore in Silicon
by Daniel Nenni on 04-30-2015 at 7:00 am

A year ago many eulogized the death of Moore’s Law at 28nm due to higher prices per transistor at more advanced nodes, but now that we have celebrated the 50th anniversary let’s look ahead to technology scaling and electronic systems miniaturization for the next decade. Despite our industry’s bipolar tendencies and daunting technical… Read More


Single Chip MCU + DSP Architecture for Automotive: SAMV71

Single Chip MCU + DSP Architecture for Automotive: SAMV71
by Eric Esteve on 04-29-2015 at 7:00 pm

It’s all about Cost of Ownership (CoO) and system level integration. If you target automotive related application, like audio or video processing or control of systems (Motor control, Inverter…) you need to integrate strong performance capable MCU with a DSP. In fact if you expect your system to support Audio Video Bridging (AVB)… Read More


Automating Timing Closure Using Interconnect IP, Physical Information

Automating Timing Closure Using Interconnect IP, Physical Information
by Majeed Ahmad on 04-29-2015 at 1:00 pm

Timing closure is a “tortoise” for some system-on-chip (SoC) designers just the way many digital guys call RF design a “black art”. Chip designers often tell horror stories of doing up to 20 back-end physical synthesis place & route (SP&R) iterations with each iteration taking a week or more. “Timing closure”, a largely… Read More


How Good Are Your Clocks?

How Good Are Your Clocks?
by Paul McLellan on 04-29-2015 at 7:00 am

One of the trickiest tasks in designing a modern SoC is getting the clock tree(s) right. The two big reasons for this:

  • the clocks can consume 30% or more of the power of the whole chip, so minimizing the number of buffers inserted is critical to keeping power under control
  • the clock insertion delay and clock skew have a major impact on
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Motley Fooled by FinFETs!

Motley Fooled by FinFETs!
by Daniel Nenni on 04-28-2015 at 10:00 pm

There was an article on Motley Fool recently detailing Intel’s 14nm FinFETs and comparing them to TSMC. Unfortunately the author has zero semiconductor education or experience even though he writes with authority on all things semiconductor. He also has no shame in using outdated papers from conferences he did not even… Read More


PDK Generation Needs Paradigm Shift

PDK Generation Needs Paradigm Shift
by Pawan Fangaria on 04-28-2015 at 4:00 pm

For any semiconductor technology node to be adopted in actual semiconductor designs, the very first step is to have a Process Design Kit (PDK) developed for that particular technology node and qualified through several design tools used in the design flow. The development of PDK has not been easy; it’s a tedious, time consuming,… Read More


Linley: Mobile Peaked in 2013?

Linley: Mobile Peaked in 2013?
by Paul McLellan on 04-28-2015 at 7:00 am

Last week was the Linley Mobile Conference. Mobile is a huge semiconductor market and, outside of Intel, is the main driver for next generation process technologies. A new generation of mobile phones comes along, fills the leading edge fabs for a year or two and then moves on to the next generation. Nothing comes close to requiring… Read More


SoC Debugging Just Got a Speed Boost

SoC Debugging Just Got a Speed Boost
by Daniel Payne on 04-28-2015 at 4:00 am

Sure, design engineers can get more attention than verification engineers, but the greater number of verification engineers on SoC projects means that the verification task is a bigger bottleneck in a schedule than pure design work. A recent survey conducted at Cadence shows how verification effort can be divided into several,… Read More