Timing closure is a “tortoise” for some system-on-chip (SoC) designers just the way many digital guys call RF design a “black art”. Chip designers often tell horror stories of doing up to 20 back-end physical synthesis place & route (SP&R) iterations with each iteration taking a week or more. “Timing closure”, a largely… Read More





How Good Are Your Clocks?
One of the trickiest tasks in designing a modern SoC is getting the clock tree(s) right. The two big reasons for this:
- the clocks can consume 30% or more of the power of the whole chip, so minimizing the number of buffers inserted is critical to keeping power under control
- the clock insertion delay and clock skew have a major impact on
Motley Fooled by FinFETs!
There was an article on Motley Fool recently detailing Intel’s 14nm FinFETs and comparing them to TSMC. Unfortunately the author has zero semiconductor education or experience even though he writes with authority on all things semiconductor. He also has no shame in using outdated papers from conferences he did not even… Read More
PDK Generation Needs Paradigm Shift
For any semiconductor technology node to be adopted in actual semiconductor designs, the very first step is to have a Process Design Kit (PDK) developed for that particular technology node and qualified through several design tools used in the design flow. The development of PDK has not been easy; it’s a tedious, time consuming,… Read More
Linley: Mobile Peaked in 2013?
Last week was the Linley Mobile Conference. Mobile is a huge semiconductor market and, outside of Intel, is the main driver for next generation process technologies. A new generation of mobile phones comes along, fills the leading edge fabs for a year or two and then moves on to the next generation. Nothing comes close to requiring… Read More
SoC Debugging Just Got a Speed Boost
Sure, design engineers can get more attention than verification engineers, but the greater number of verification engineers on SoC projects means that the verification task is a bigger bottleneck in a schedule than pure design work. A recent survey conducted at Cadence shows how verification effort can be divided into several,… Read More
The 2015 DAC Designer and IP Track
What an exciting year for DAC with record submissions in nearly every category. Most impressive is the increase in Designer and IP Track submissions, content that is helping to continue to evolve and improve the show. If you haven’t already registered, why not do so now?
A brief bit of background about the conference: DAC’s roots… Read More
Four Reasons Why Atmel is Ready to Ride the IoT Wave
In 2014, a Goldman Sachs’ report took many people by surprise when it picked Atmel Corp. as the company best positioned to take advantage of the rising Internet of Things (IoT) tsunami. At the same time, the report omitted tech industry giants like Apple and Google from the list of companies that could make a significant impact… Read More
A Vision for FPGA Prototyping Realized
FPGA prototyping is beginning its move to the forefront of design and verification. More and more companies are turning to this technology not only for in-circuit testing and earlier software development but also for refining, validating, and implementing chip architecture. The increases in design size and complexity as well… Read More
Semiwiki Blogger at DAC: MIPI Beyond Mobile, Myth or Reality?
Some of the various MIPI specifications are now massively used in mobile (smartphone or tablet), especially the Multimedia related specs like Camera Serial Interface (CSI-2), Display Serial Interface (DSI) or SoundWire (even if the spec has been released in December 2014, the adoption rate is very sharp, no doubt that it will… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot