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Predictions about EDA and IP at #52DAC

Predictions about EDA and IP at #52DAC
by Daniel Payne on 06-10-2015 at 4:00 am

On Sunday night at DAC this week I sat in the front row and listened to Gary Smith give his predictions about EDA and IP as an industry. His financial forecast was a $6.8B industry in 2015, growing to $9B in 2019. An ideal company for Wall Street to invest in would have slow and steady growth. If you add semiconductor IP into the forecast… Read More


Google Smart Lens: IC Design and Beyond

Google Smart Lens: IC Design and Beyond
by Paul McLellan on 06-09-2015 at 1:00 am

Today’s DAC keynote was by Brian Otis of Google about their project, working with Novartis, to build disposable contact lenses that perform continuous glucose monitoring.

Why is this important? There are 382M people around the world with diabetes who typically have to check their blood glucose levels four times a day. … Read More


EDA Acquisition to Drive SoC realization

EDA Acquisition to Drive SoC realization
by Pawan Fangaria on 06-08-2015 at 8:00 pm

A week ago I was reading an article written by Daniel Nenni where he emphasised about semiconductor acquisitions to fuel innovation. We would see that in a larger space, not only in semiconductor and FPGA manufacturing companies (e.g. Intel and Altera) but also in the whole semiconductor ecosystem. If we see it from technical perspective,… Read More


TSMC Shows 10nm Wafer!

TSMC Shows 10nm Wafer!
by Daniel Nenni on 06-08-2015 at 4:00 pm

If you really want to know why I write about TSMC it is all about ego, my massive ego, absolutely. Blogs about TSMC and the foundries have always driven the most traffic and they most likely always will. Semiconductor IP is second, Semiconductor Design is third, and I don’t think that is going to change anytime soon:

SemiWiki BI: DanielRead More


Next Generation Formal Technology to Boost Verification

Next Generation Formal Technology to Boost Verification
by Pawan Fangaria on 06-08-2015 at 12:00 pm

With growing complexities and sizes of SoCs, verification has become a key challenge for design closure. There isn’t a single methodology that can provide complete verification closure for an SoC. Moreover creation of verification environment including hardware, software, testbench and testcases requires significant … Read More


Synopsys to Acquire Atrenta

Synopsys to Acquire Atrenta
by Paul McLellan on 06-07-2015 at 11:17 pm

I was at the DAC kickoff this evening in the Intercontinental Hotel. I was talking to Dave DeMaria, the senior marketing guy at Synopsys and he told me of a couple of minor press releases due to hit the wire tomorrow morning, didn’t sound important enough to be blogworthy. Aart was there too although I didn’t speak to him.… Read More


5 Things Chipmakers Are Missing on the IoT

5 Things Chipmakers Are Missing on the IoT
by Don Dingee on 06-07-2015 at 7:00 pm

When the RISC movement surfaced in 1982, researchers analyzed UNIX to discover what instructions multi-user code was actually using, and then designed an instruction set and execution pipeline to do that better. Fewer instructions meant fewer transistors, which led to less power consumption – although in the original… Read More


Turning the Automotive Development Process Upside Down

Turning the Automotive Development Process Upside Down
by Daniel Payne on 06-07-2015 at 2:00 pm

Most of us drive automobiles and have a vague idea that the development of our cars takes many years, millions of dollars, is a proprietary process and require huge factories to produce. A relatively new company called Local Motors founded in 2007 has started to turn the automotive development process upside down because they do… Read More


ESD Protection Network Checking is Difficult But Necessary

ESD Protection Network Checking is Difficult But Necessary
by Tom Simon on 06-06-2015 at 6:00 pm

I’ve written before about anti-fuse non-volatile memory, where the gate oxide is intentionally damaged in order to create a readable bit of data, but this is what most circuit designers never want to have happen to their logic gates. However, since the advent of MOS transistors the issue of Electrostatic Discharge (ESD) and the… Read More


Vacationing with the Fabless Semiconductor Ecosystem!

Vacationing with the Fabless Semiconductor Ecosystem!
by Daniel Nenni on 06-05-2015 at 4:00 pm

The Design Automation Conference is the largest and most diverse event in the fabless semiconductor ecosystem. Next week in San Francisco you will see technology and people you have never seen before. You will benefit from the efforts of hundreds of thousands of semiconductor professionals like myself who have dedicated their… Read More