Probably one of the most awaited semiconductor events is coming next week if the Poughkeepsie Journal is correct, which from what I’m told by my Albany friends, they are. The official announcement was made last October using the slide deck which can be found HERE. It was originally thought that the approval process would take a year… Read More



Unlock the Key to Ultra-Low Power Design
We have been hearing about low power for a long time. Fortunately, low power chip operation has come about through a large number of innovations. Key among these is clock gating, frequency and voltage scaling, managing leakage with lower threshold voltage, HKMG, and many other techniques. But we are entering the age of ultra low… Read More
An Universe of Formats for IP Validation
Although I knew about Crossfire’s capabilities for signing off quality of an IP before its integration into an SoC, there was much more to learn about this tool when I visited Fractal Technologies booth during this DAC. The complexity handled by this tool to qualify any type of IP for its integration into an SoC can be imagined by the… Read More
IBM Design Tools in the Cloud: Big News or Old News?
One announcement that I missed coming up to the Design Automation Conference last week was that SiCAD is hosting a portfolio of IBM’s design automation tools in the cloud. Supposedly these are priced half the cost of similar capability from Cadence, Synopsys and Mentor. So should the big three be worried? Is this an earth-shattering… Read More
Solido Has Perfected the Emerging EDA Company Business Model!
Last year at #51DAC we gave away more than a thousand printed versions of our book “Fabless: The Transformation of the Semiconductor industry.” This year we gave away pens with a light and stylus. My friends at Solido Design gave away 600 pens in their booth and we gave away another 400 at our DAC reception on Wednesday night. Solido… Read More
Can FD-SOI Change the Rule of Game?
It appears so. Why there is so much rush towards FD-SOI in recent days? Before talking about the game, let me reflect a bit on the FD-SOI technology first. The FD-SOI at 28nm claims to be the most power-efficient and lesser cost technology compared to any other technology available at that node. There are many other advantages from… Read More
Semiconductor Equipment: the Report and the Show
Somebody said to me recently that SEMICON West, which takes place in San Francisco July 14-16th, isn’t that big a deal since very little manufacturing goes on in the US any more. In fact 15% of manufacturing capacity is in north america (I think that actually means the US since I don’t think there are any fabs in Canada).… Read More
The Best Conversations You Missed at #52DAC!
The CEO Fireside Chats were my very favorite part of #52DAC. Dr. Walden Rhines, Lip-Bu Tan, and Dr. Aart de Geus are heroes of the EDA industry, absolutely. I saw all three Fireside Chats and the one word that I’m left with is INSPIRED! … Read More
DDR stands for Don’t Do (Just) RTL
In optimizing SoC design for performance, there is so much focus on how fast a CPU core is, or a GPU core, or peripherals, or even the efficiency of the chip-level interconnect. Most designers also understand selecting high performance memory at a cost sweet spot, and optimizing physical layout to clock it as fast as possible within… Read More
Apple Watch Design Revisit with a Wi-Fi Twist
Apple Watch is the world’s most celebrated gadget in 2015. At the same time, however, early product reviews highlight some issues about slow apps, less than impressive user experience, and short battery life.
Apple, the master of artful integration, has done well for its reputation of elite hardware and has been able to … Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot