On the first two chapters of this Tutorial we started with a simple LFSR module and added a test bench. Then, on chapters three and four we upgraded our module with some features and learned to export the test bench data to files.
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Power-SOI: The Reliability Engine Behind Functional Safety ICsPower-SOI technology is rapidly emerging as a foundational…Read More
ASML High-NA EUV is Not Ready for High-Volume ProductionContrary to the popular press, ASML High-NA EUV…Read More
What Winemakers and Chip Designers Have in CommonConsider this a standout presentation at the Silicon…Read More
Learn How llmda Uses Agentic AI to Generate Hardware Docs & Keep Them ConsistentAccurate, complete, and consistent technical documentation is a…Read MorePseudo random generator tutorial in VHDL (Part 2/3)
In the first part of this tutorialwe started with a simple implementation of an LFSR block (Chapter 1) and its test bench (Chapter 2). Let’s make our code look a bit more professional.
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Pseudo random generator tutorial in VHDL (Part 1/3)
In this tutorial we will see how to design a VHDL block. We will start with a very simple block and we will gradually add features to it. We will also simulate it and test its output with Matlab. Over the process we will see:
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The 2016 Leading Edge Semiconductor Landscape
The leading edge semiconductor logic landscape has in recent years collapsed to just four companies. The following is a summary of what is currently known about each company’s plans and how they compare. ASML has analyzed many logic nodes and developed a formula that normalizes processes to a “standard node”.… Read More
Pushing automotive-grade embedded flash to 28nm
18 months ago Renesas announced they were prototyping their SG-MONOS eFlash on 28nm, and at the time we said it would be a couple of years before actual product. Yesterday, Renesas revealed their partner in this effort is TSMC – no surprise – and hinted things are moving, with better performance than expected but on a longer qualification… Read More
Five Things To See at DVCon India 2016
DVCon is an annual Design and Verification Conference that started out in Silicon Valley, then expanded by adding India as a new location. Our semiconductor design and verification world is global in stature, so if you’re living in the region then consider registering for this event held Thursday and Friday, September … Read More
Petahertz Electronics?
In the early days of integrated components, we used to think kHz (~10[SUP]3[/SUP]Hz) processing was pretty wild. Those systems were quickly eclipsed by MHz (~10[SUP]6[/SUP]Hz) performers and now we’re blasé about GHz (~10[SUP]9[/SUP]Hz) speeds. Recently (2014), DARPA announced a THz (~10[SUP]12[/SUP]Hz) amplifier, built… Read More
TSMC Fab 12 is a Pokemon Go Stop!
It only seems fitting that Fab 12 is a PokeStop since TSMC stands to make a lot of money from the augmented reality gaming craze that is sweeping the world. Unfortunately, most of the press I have read about Pokemon Go has been negative but that is the new “negative media” world we live in. As a player myself (level 25) and a semiconductor… Read More
Time for U.S. Fatality Reduction Targets
Almost exactly a year ago I wrote a blog implicating the insurance industry in the high level of highway fatalities in the U.S. As part of that blog (“The Insurance Industry Has Blood on Its Hands”) I suggested that the National Highway Traffic Safety Administration ought to look into developing a fatality-reduction… Read More
Is Your Next Reality Going to be Augmented?
John Lennon reportedly once said “Reality leaves a lot to the imagination…” and now we have the technology to do something about making our reality a lot more imaginative. Unless you have been living under a rock (and there is nothing wrong with that – I just haven’t found the right rock myself) there is a LOT going on these days in the… Read More


SoC PLANNER: A New Generation of SoC Design Exploration Solution Managing Cost-effectiveness and Sustainability