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VC For Semiconductor: Dead or Alive?

VC For Semiconductor: Dead or Alive?
by Paul McLellan on 07-14-2015 at 7:00 am

By Charlie Cheng, CEO of Kilopass.

Six years ago, I left my Entrepreneur-In-Residence (EIR) role at a venture capital firm to join Kilopass as an “interim CEO”, thinking the venture world will eventually forget about semiconductor as an industry as it matures. So it’s interesting to me how, six years later, the venture investment… Read More


Improve RTL Physically for Design Quality & Convergence

Improve RTL Physically for Design Quality & Convergence
by Pawan Fangaria on 07-13-2015 at 12:00 pm

The SoC design teams are usually divided between front-end and back-end specialties. It is neither practical nor advisable to combine the two teams in order to better tackle the back-end issues upfront during the front-end design. However, a common problem is that the issues at the layout stage have very little scope for resolution… Read More


Silicon Saxony!

Silicon Saxony!
by Daniel Nenni on 07-13-2015 at 8:00 am

The “Saxony” reference comes from the Holy Roman era which is now the tenth largest of Germany’s sixteen states and is divided into ten districts. The “Silicon” comes from the microchip makers in the Dresden area which is district #2. The largest of said chip makers is now GlobalFoundries so in the same vein that California has Silicon… Read More


GlobalFoundries FD-SOI. Yes, It’s True

GlobalFoundries FD-SOI. Yes, It’s True
by Paul McLellan on 07-13-2015 at 6:00 am

There have been rumors around for months (even on Semiwiki here) but today it is official. GlobalFoundries announced 22FDX which is a 22nm FD-SOI platform. GF announced that they had licensed FD-SOI from STMicroelectronics a couple of years ago and then…nothing. I just assumed it was a marketing deal that would be driven… Read More


In Memoriam Gary Smith

In Memoriam Gary Smith
by Paul McLellan on 07-12-2015 at 8:00 pm

EDA rallied today for one of their own, without caring which company any of us worked for. We even got together in a ballroom in the San Jose Doubletree that I’m sure many of us have been in many times to endure way too many powerpoint slides at EDA conferences held there over the years. The instructions were to wear orange. At least… Read More


Conquering the Next IoT Challenges with FPGA-Based Prototyping

Conquering the Next IoT Challenges with FPGA-Based Prototyping
by Daniel Nenni on 07-12-2015 at 12:00 pm

The need for ever-connected devices is skyrocketing. As I fiddle with my myriad of electronic devices that seem to power my life, I usually end up wishing that all of them could be interconnected and controlled through the Internet. The truth is, only a handful of my devices are able to fulfill that wish, but the need is there and developers… Read More


Surprisingly Phablets Bucking the Trend

Surprisingly Phablets Bucking the Trend
by Pawan Fangaria on 07-12-2015 at 7:00 am

Amid a fiercely competitive market for computing devices, smartphones, tablets, and so on, a number of devices were created in this decade to invade into each other’s functionalities to either eat away other’s market share or retain their own. The key contenders were smartphones, Phablets, tablets and mini notebooks, whereas… Read More


Who Needs to Lead at the 14, 10 and 7nm nodes

Who Needs to Lead at the 14, 10 and 7nm nodes
by Scotten Jones on 07-11-2015 at 12:00 pm

IBM recently disclosed a working 7nm test chip generating a lot of excitement in the semiconductor industry and also in the mainstream media. In this article I wanted to explore the 14nm, 10nm and 7nm nodes, the status of the key competitors at each node and what it may mean for the companies.

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Which High B/W Memory to Select after DDR4?

Which High B/W Memory to Select after DDR4?
by Eric Esteve on 07-11-2015 at 6:00 am

Once upon a time, RAM technology was the driver of the semiconductor process. DRAM products were the first to be designed on a newest technology node and DRAM was used as a process driver. It was 30 years ago and the most aggressive process nodes were ranging between 1um and 1.5 um (1 500 nm!). Then in the 1990 the Synchronous Dynamic … Read More


Tackling Layout Gradient Effects in 16 nm FinFET using Layout Automation

Tackling Layout Gradient Effects in 16 nm FinFET using Layout Automation
by Daniel Payne on 07-10-2015 at 12:00 pm

My first exposure to automating IC layout was back in the 1980’s at Intel where I coded a layout compiler to auto-generate about 6% of a graphics processor chip. The need to use automation for IC layout continues today, and with the advent of FinFET technology there are some new challenges like layout gradient effects that … Read More