Synopsys Webinar – Enabling Multi-Die Design with IntelAs we all know, the age of multi-die…Read More
Materials Selection Methodology White PaperThe Granta EduPack White Paper on Materials Selection,…Read More
Formal Verification: Why It Matters for Post-Quantum CryptographyFormal verification is becoming essential in the design…Read More
Architecting Your Next SoC: Join the Live Discussion on Tradeoffs, IP, and Ecosystem RealitiesDesigning a system-on-chip (SoC) has never been more…Read More
SiFive held a RISC-V Technology Symposium on February 26 at the Computer History Museum in Mountain View. Keith Witek, SiFive SVP Corporate Development and Strategy kicked off the event and introduced the first keynote speaker Martin Fink, Western Digital CTO, at the time acting CEO of the RISC-V Foundation (as of this writing,… Read More
There was an interesting keynote at DVCon last month. It was titled “Thriving in the Age of Digitalization” which introduced the concept of digital twins for design and production. It was presented by Fram Akiki who is a relative newcomer to EDA but has an interesting history so I will start there.
Fram and I got started in the semiconductor… Read More
I have gazed across the Pond in bafflement over Brexit until two days ago. I now grasp the depth and breadth of British anxiety over political and legal ties to Brussels and it boils down to regulatory over-reach.
Yesterday, the European Commission announced that it had adopted new rules “stepping up the deployment of Cooperative… Read More
On April 2 – 4, the 2019 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics (FCMN) will be held at the Monterey Marriott in Monterey, CA. The 2019 FCMN is the 12th in the series that began in 1995 with a keynote talk by Craig Barrett, ex-CEO of Intel.… Read More
I had a chat with Bob Smith, Executive Director of ESD Alliance, about the upcoming SEMI conference in China. More than 100,000 people are expected to attend which is beyond my comprehension. SEMICON in San Francisco is maybe 20,000 people which is the largest conference I attend. I’m not sure if the Design Automation Conference… Read More
The IC design and verification process can be comprised of many independent point tools, or for more synergy you can have tools that work together by a more synergistic process. We’ve all heard the maxim, “Work smarter, not harder.” A white paper just came out from Methodics on a smarter approach, Traceability… Read More
As you may know, Silvaco has done some very clever acquisitions to fuel their unprecedented growth over the last five years. We have a wiki that tracks EDA Mergers and Acquisitions, Silvaco included, and it is the most viewed wiki on SemiWiki.com with 102,005 views thus far.
Silvaco acquired Nangate in March of 2018. NanGate got … Read More
One of the great pleasures in what I do is to work with people who are working with people in some of the hottest design areas today. A second-level indirect to be sure but that gives me the luxury of taking a broad view. A recent discussion I had with Kurt Shuler (VP Marketing at Arteris IP) is in this class. As a conscientious marketing… Read More
One of the key growth areas for the semiconductor ecosystem is IP which of course includes IP related EDA software. In May of 2017 design management/collaboration expert (one of my personal favorite EDA companies) ClioSoft announced designHUB[SUP]®[/SUP] for IP management and re-use. Using designHUB, semiconductor companies… Read More
I think Synopsys would agree that they were not an early entrant to the emulation game, but once they really got moving, they’ve been working hard to catch up and even overtake in some areas. A recent webinar highlighted work they have been doing to overcome a common challenge in this area. Being able to boot a billion-gate design, … Read More
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