About once a quarter, I touch base with Cristian Amitroaie, CEO and co-founder of AMIQ EDA, to see what’s new with the company, products, and users. Sometimes he surprises me, as he did earlier this year when he mentioned that their tools check about 150 rules for non-standard constructs in SystemVerilog and VHDL. When we talked … Read More
Webinar: Why AI-Assisted Security Verification For Chip Design is So ImportantIt is well-known that AI is everywhere, and…Read More
Nvidia Overcoming the Challenges of Blending Hardware Verification Expertise with AI and ML Verification Futures Conference 2025…Read More
Automotive Digital Twins Out of The Box and Real Time with PAVE360Digital twins are amazing technology, virtual representations mirroring…Read MoreNeural Nets and CR Testing. Innovation in Verification
Leveraging neural nets and CR testing isn’t as simple as we first thought. But is that the last word in combining these two techniques? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research ideas. As always, feedback welcome.… Read More
Webinar: Learn about NVMe conformance Testing
Several years ago I recall upgrading my aging MacBook Pro laptop from using a Hard Disk Drive (HDD) to a Solid State Drive (SSD) that used Non-Volatile Memory (NVM). Oh what a speed improvement when pushing that On button each morning to start the work day, or clicking an App to see it launch without delay. Another epiphany for me in … Read More
Siemens Offers Insights into Gate Level CDC Analysis
Glitches on clock domain crossing signals have always been a concern for chip designers. Now with increased requirements for reliability, renewed scrutiny is being given to find ways to identify these problems and fix them. In particular applications such as automotive electronics have given this added effort an impetus. Siemens… Read More
Keynote from Air Force Research Laboratory at CadenceLIVE Americas 2021
Cadence hosted its annual CadenceLIVE Americas conference June 8th-June 9th. Four keynotes and eighty-three different talks on various topics were presented. The talks were delivered by Cadence, its customers and partners.
The C-suite keynotes were delivered by Lip-Bu Tan (CEO) and Dr. Anirudh Devgan (President). The talks… Read More
COVID Recovery Revalues Vision Data
As the U.S. and global economies emerge from COVID-19 lockdowns the enduring impact on transportation is still unfolding. Ride hail drivers are returning. Car sharing is surging. Autonomous vehicle testing is reviving. Commuters are commuting. And pedestrians are multiplying.
As people and vehicles return to highways
A Free RISC-V CPU Core Builder – Democratizing CPUs
There are now over a hundred RISC-V CPU cores listed on riscv.org‘s RISC-V Exchange! Amazing. If you need a RISC-V CPU core, you’ll likely be able to find one that suits your needs… if you evaluate a hundred CPU cores to find it.
Or, now, you can configure exactly the core you need, and have it built in seconds, for free! WARP-V … Read More
Podcast EP26: The Challenges and Opportunities of IP Reuse
Dan and Mike are joined by Simon Rance, head of marketing for Cliosoft. Simon discusses a broad range of topics associated with IP reuse, from the IP provider and IP consumer point of view. Design data management, as well as IP technical capabilities, license tracking and the benefits of a knowledge base and more are reviewed.
The
CEO Interview: Sivakumar P R of Maven Silicon
Sivakumar P R is the Founder and CEO of Maven Silicon. He is responsible for the company’s vision, overall strategy, business, and technology. He is also the Founder and CEO of Aceic Design Technologies.
Sivakumar is a seasoned engineering professional who has worked in various fields, including electrical engineering,… Read More
Circuit Simulation Challenges to Design the Xilinx Versal ACAP
One of the most unique acronyms that I learned about this past year is ACAP from Xilinx, which stands for Adaptive Compute Acceleration Platform. At the recent Cadence LIVE event, I had the pleasure of watching Pei Yao, a Xilinx senior staff CAD engineer, as she talked about the challenges of getting all the analog and mixed-signals… Read More




AI Bubble?