TSMC's 2024 Sustainability Report: Pioneering a Greener Semiconductor FutureTSMC, the world's most trusted semiconductor foundry, released…Read More
Intel's Commitment to Corporate Responsibility: Driving Innovation and SustainabilityIntroduction by Lip-BU Tan: I’m an engineer at…Read More
Cadence's Strategic Leap: Acquiring Hexagon's Design & Engineering BusinessIn a bold move that underscores the accelerating…Read More
TSMC 2025 Update: Riding the AI Wave Amid Global ExpansionWelcome to the second half of a very…Read More
Alchip’s 3DIC Test Chip: A Leap Forward for AI and HPC InnovationToday Alchip Technologies, a Taipei-based leader in high-performance…Read More
On Sep 20th, Synopsys announced an expansion of its DesignWare® ARC® Processor IP portfolio with new 128-bit ARC VPX2 and 256-bit ARC VPX3 DSP Processors targeting low-power embedded SoCs. In 2019, the company had launched a 512-bit ARC VPX5 DSP processor for high-performance signal processing SoCs. Due to the length, format… Read More
Verification is a complex task that takes the majority of time and effort in chip design. Veriest shares customer views on what this means. We are an ASIC services company, and we have the opportunity to work on multiple projects and methodologies, interfacing with different experts.
In this “Verification Talks”… Read More
The shortage of semiconductors for automotive applications is getting worse. Recent statements from major automakers:
A processor ISA provides an abstraction against which to verify an implementation. We look here at a paper extending this concept to accelerators, for verification of how these interact with processors and software. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys… Read More
My first IR drop analysis was back in the early 1980s at Intel, where I had to manually model the parasitics of the VDD and VSS interconnect for all of the IO cells that our team was designing in a graphics chip, then I ran that netlist in a SPICE simulator using transient analysis, measuring the bounce in VSS and droop in VDD levels as all… Read More
Anyone can create a testbench[TB] and verify the design, but it can’t be simply reused as a verification IP [VIP]. So I would like to address in this article: What is VIP? How can we build a high-quality VIP? How can we verify the VIP? What else can we do to make the VIP unique and commercially more valuable?
Most of the module/IP level … Read More
I’ve simulated IC designs at the transistor-level with SPICE, gate-level, RTL with Verilog, and even used cycle-based functional simulators. Sure, they each worked well, but only for the domain and purpose they were designed for. Industry analyst, Gary Smith predicted that the IC world would soon move to system-level… Read More
In June 2021, eMemory Technology hosted a webinar titled “PUFiot: A PUFrt-based Secure Coprocessor.” You can read a blog leading up to that webinar here. PUFiot is a novel high-security crypto coprocessor. You can access a recording of that entire webinar from eMemory’s Resources page. While the focus of that webinar was to present… Read More
The field of DRAM is fascinating as it continues to grow and innovate. For the past ten years, I have often read that DRAM is running out of steam because of its difficulty to scale the capacitor, and yet it continues to evolve since invented by Dr. R. Dennard at IBM. In 1966, he introduced the concept of a transistor memory cell consisting… Read More
I knew something special was going on in Munich last week at IAA Mobility – the first international auto show to be held outside China since the start of the pandemic – when a senior executive stepped off the stage before his talk to a modest crowd to say to me (sitting in the second row): “What are you doing here?” I don’t remember whether… Read More
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Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet