Taming Concurrency: A New Era of Debugging Multithreaded CodeAs modern computing systems evolve toward greater parallelism,…Read More
Perforce Webinar: Can You Trust GenAI for Your Next Chip Design?GenAI is certainly changing the world. Every day…Read More
A Principled AI Path to Spec-Driven VerificationI have seen a flood of verification announcements…Read More
448G: Ready or not, here it comes!The march toward higher-speed networking continues to be…Read More
Should the US Government Invest in Intel?“Most companies don’t die because they are wrong;…Read More
We used to be comfortable with the idea that the worlds of logical design and physical implementation could be largely separated. Toss the logical design over the wall, and the synthesis and P&R teams would take care of the rest. That idea took a bit of a hit when we realized that synthesis had to become physically aware. The synthesis… Read More
Recently, a patent application from TSMC [1] revealed target EUV doses used in the range of 30-45 mJ/cm2. However, it was also acknowledged in the same application that such doses were too low to prevent defects and roughness. Recent studies [2,3] have shown that by considering photon density along with blur, the associated shot… Read More
Verification is a complex task that takes the majority of time and effort in chip design. At Veriest, as an ASIC services company, we have the opportunity to work on multiple projects and methodologies, interfacing with different experts.
In this “Verification Talks” series of articles, we aim to leverage this unique… Read More
Frequent SemiWiki readers are aware of the growing significance of heterogeneous multi-die packaging technologies, offering a unique opportunity to optimize system-level architectures and implementations. The system performance, power dissipation, and area/volume (PPA/V) characteristics of a multi-die… Read More
Lam- good quarter but supply chain headwinds limit upside
Memory seems OK for now but watch pricing
China will also weaken which may add caution
Performance remains solid as does technology prowess
The yellow caution flag in the Semi race impacts Lam as well
As we suggested two weeks ago and saw with ASML this morning, supply chain… Read More
ASML great QTR but supply chain will limit acceleration
Products are most complex with most extensive supply chain
Long term position fantastic but investors will be nervous
300M pushouts in DUV with EUV still on track
Good quarter but yellow caution flag is out for supply chain concerns
ASML reported great revenues of Euro5.2B… Read More
Dan and Mike are joined by Kim McMahon, Director of Visibility & Community Engagement, RISC-V International and Rob Mains Executive Director, CHIPS Alliance. Kim and Rob are working with individuals and companies to promote diversity and inclusion in the open hardware industry. We explore their strategies, goals and plans… Read More
Jothy Rosenberg is a serial entrepreneur, founding nine different startups since 1988, two of which sold for over $100M. Currently, he’s the Founder & CEO of Dover Microsystems, the first oversight system company. Earlier in his career, Jothy ran Borland’s Languages division where he managed languages like Delphi, C++,… Read More
SoC design for security has grown and evolved over time to address numerous potential threat sources. Many countermeasures have arisen to deal with ways hackers can gain control of systems through software or hardware design flaws. The results are things like improved random number generators, secure key storage, crypto, and… Read More
Using FPGAs to prototype and debug SoCs as part of the SoC design verification hierarchy was pioneered by Quickturn Design Systems in the late 1980’s, and I have observed a wide variety of FPGA prototyping projects over the years. In retrospect, three factors have determined the success of the FPGA prototyping project;
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Should the US Government Invest in Intel?