Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High-Performance RISC-V CPUsFor decades, high-performance CPU design has been dominated…Read More
Orchestrating IC verification: Harmonize complexity for faster time-to-marketBy Marko Suominen and Slava Zhuchenya of Siemens…Read MoreBasilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status QuoAt Hot Chips 2025, Philippe Sauter of ETH…Read More
GlobalFoundries 2025 Update GTS25"GTS25 brings together leaders from across the semiconductor…Read More
The 5nm foundry node saw the arrival of 6-track standard cells with four narrow routing tracks between wide power/ground rails (Figure 1a), with minimum pitches of around 30 nm [1]. The routing tracks require cuts [2] with widths comparable to the minimum half-pitch, to enable the via connections to the next metal layer with the… Read More
Dan is joined by Dr. Matthew Commens, product manager Ansys. Matt discusses an upcoming webinar series on the inner workings and capabilities of Ansys simulation software. How the series began, the impact and benefits and a view of the future are all covered.
Webinar Series: Learn the Foundation of Computational Electromagnetics… Read More
We all know that designers work hard to reach design closure on SOC designs. However, what gets less attention from consumers is the effort that goes into ensuring that these chips will be fully operational and meeting timing specs over their projected lifetime. Of course, this is less important for chips used in devices with projected… Read More
The outlook for electronics and semiconductors in 2022 is uncertain. Just as the world was returning to more normal conditions after (hopefully) the worst of the COVID-19 pandemic is over, Russia invaded Ukraine in February.
The International Monetary Fund (IMF) in a March 15 blog post asserted the Russian invasion of Ukraine… Read More
Compared to the automation of digital design, the development of automation for analog has taken a much more arduous path. Over the decades there have been many projects both academic and commercial to accelerate and improve the process for analog design. One of the most interesting efforts in this area is being spearheaded by … Read More
There is sometimes an irony in switching to a better solution in design construction or analysis. The new approach is so much better that you want to experiment to further optimize the design. Which then exposes another barrier to enjoying that newfound freedom. SoC design teams often find this when switching from crossbar interconnect… Read More
I was recently updating an analysis I did last year that looked at EUV system supply and demand, while doing this I started thinking about Intel and their Fab portfolio.
If you look at Intel’s history as a microprocessor manufacturer, they are typically ramping up their newest process node (n), in volume production… Read More
Advanced semiconductor nanometer technology nodes, together with smart IC design applications enable today very complex and powerful systems for communication, automotive, data transmission, AI, IoT, medical, industry, energy harvesting, and many more.
However, more aggressive time-to-market and higher performance… Read More
With ever challenging time to market requirements, co-developing IP and firmware is imperative for all system development projects. But that doesn’t make the task any easier. Depending on the complexity of the system being developed, the task gets tougher. For example, different pieces of IP may be the output of various teams… Read More
AI/ML functions are moving to the edge to save power and reduce latency. This enables local processing without the overhead of transmitting large volumes of data over power hungry and slow communication links to servers in the cloud. Of course, the cloud offers high performance and capacity for processing the workloads. Yet, … Read More
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Intel’s Pearl Harbor Moment