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New ECO Product – Synopsys PrimeClosure

New ECO Product – Synopsys PrimeClosure
by Daniel Payne on 09-29-2022 at 10:00 am

ECO types min

New EDA product launches are always an exciting time, and I could hear the energy and optimism from the voice of Manoj Chacko at Synopsys in our Zoom call about Synopsys PrimeClosure. During the physical implementation phase for IC designs there’s a big challenge to reach timing closure, and with advanced nodes the number… Read More


Test Ordering for Agile. Innovation in Verification

Test Ordering for Agile. Innovation in Verification
by Bernard Murphy on 09-29-2022 at 6:00 am

Innovation New

Can we order regression tests for continuous integration (CI) flows, minimizing time between code commits and feedback on failures? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas.… Read More


Whatever Happened to the Big 5G Airport Controversy? Plus A Look To The Future

Whatever Happened to the Big 5G Airport Controversy? Plus A Look To The Future
by Josh Salant on 09-28-2022 at 10:00 am

Figure1 2

In December 2021, just weeks before Verizon and AT&T were set to enable their new radio access networks in the 5G mid-band spectrum (also known as C-Band), the Federal Aviation Administration (FAA) released a Special Airworthiness Information Bulletin (SAIB) and a statement notifying operators of potential 5G interference… Read More


WEBINAR: How to Accelerate Ansys RedHawk-SC in the Cloud

WEBINAR: How to Accelerate Ansys RedHawk-SC in the Cloud
by Daniel Nenni on 09-28-2022 at 8:00 am

How to Accelerate Ansys RedHawk SC in the Cloud

 

As we all know, growing complexity of IC designs and the resulting numbers of EDA tools and design steps lead to very intricate workflows which require compute cycles that outstrip current compute capacity of most IC enterprises. The obvious question is how to efficiently leverage near infinite compute capacity in the … Read More


Arm and Arteris Partner on Automotive

Arm and Arteris Partner on Automotive
by Bernard Murphy on 09-28-2022 at 6:00 am

Arteris Arm partnership

Whenever a new partnership is announced, the natural question is, “why?” What will this partnership make possible that wasn’t already possible with those two companies working independently? I talked yesterday with Frank Schirrmeister of Arteris on the partnership. (Yes, Frank is now at Arteris). And I just got off an Arm press… Read More


3D IC – Managing the System-level Netlist

3D IC – Managing the System-level Netlist
by Daniel Payne on 09-27-2022 at 10:00 am

2.5D IC min

I just did a Google search for “3D IC”, and was stunned to see it return a whopping 476,000 results. This topic is trending, because more companies are using advanced IC packaging to meet their requirements, and yet the engineers doing the 3D IC design have new challenges to overcome. One of those challenges is creating… Read More


Arm 2022 Neoverse Update, Roadmap

Arm 2022 Neoverse Update, Roadmap
by Bernard Murphy on 09-27-2022 at 6:00 am

Neoverse update min

Arm recently provided their annual update on the Neoverse product line, targeting infrastructure from cloud to communication to the edge. Chris Bergey (SVP and GM for infrastructure) led the update, starting with a shock-and-awe pitch on Neoverse deployment. He played up that Arm-based servers are now in every major public … Read More


UCIe Specification Streamlines Multi-Die System Design with Chiplets

UCIe Specification Streamlines Multi-Die System Design with Chiplets
by Dave Bursky on 09-26-2022 at 10:00 am

protocol stack 1

Over the last few years, the design of application-specific ICs as well as high-performance CPUs and other complex ICs has hit a proverbial wall. This wall is built from several issues: first, chip sizes have grown so large that they can fill the entire mask reticle and that could limit future growth. Second, the large chip size impacts… Read More


Methodology to Minimize the Impact of Duty Cycle Distortion in Clock Distribution Networks

Methodology to Minimize the Impact of Duty Cycle Distortion in Clock Distribution Networks
by Kalar Rajendiran on 09-26-2022 at 6:00 am

Figure Gate Failing to Reach 1.1V

Synchronous circuits dominate the electronic world because clocking eases the design of circuits compared to asynchronous circuits. At the same time, clocking also introduces its share of challenges to overcome. No wonder, a tremendous amount of time and effort have been spent over the years on developing and implementing … Read More


Podcast EP108: Brief History of the Semiconductor Industry – How Did It Get Started?

Podcast EP108: Brief History of the Semiconductor Industry – How Did It Get Started?
by Daniel Nenni on 09-23-2022 at 10:05 am

Dan is joined by Chris Miller, Associate Professor of International History at The Fletcher School and author of Chip War: The Fight for the World’s Most Critical Technology, a geopolitical history of the computer chip. Chris provides a far-reaching overview of the forces that shaped the worldwide semiconductor industry,… Read More