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Verification Engineer (DDR)

Verification Engineer (DDR)
by Admin on 07-12-2023 at 3:47 pm

Website Achronix

Job Description/Responsibilities

The successful candidate will contribute to the verification and validation of FPGA cores and related ASIC subsystems implemented in modern FPGA technology nodes (16nm, 7nm and below). Responsibilities include:

  • Verify ASIC logic subsystems developed for high-speed networking and data center applications for inclusion in modern FPGAs
  • Define and review verification plans and tests in collaboration with the design team
  • Develop automated processes for block- and system-level development and verification
  • Implement functional coverage and enhance the testbench to ensure coverage closure
  • Contribute to customer deliverables related to verification and device modeling
  • Collaborate with internal and external team members on architectural decisions, development flows and methodologies
  • Contribute to device bring-up and Post-Silicon validation

Required Skills

  • Strong knowledge of Verilog, SystemVerilog, and Object-Oriented Programming
  • Experience with modern Pre-Silicon verification techniques, especially including SystemVerilog, UVM, constraint-random and functional coverage methodologies
  • Complete understanding of verification life cycle and ability to create comprehensive verification plans
  • Knowledge of high-speed interconnect, AXI, APB, AHB protocols
  • Solid understanding of high-performance memory subsystem architectures with related experience
  • Experience verifying memory controllers and PHYs against cutting edge JEDEC DDR protocols
  • Experience verifying memory RAS features such as ECC, CRC, and scrubbing
  • Knowledge of types of PHY training algorithms and tester algorithms, as well as diagnostic and debug mechanisms
  • Experience with scripting languages such as Python, Tcl, or Perl
  • Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out
  • Strong technical writing and verbal communication skills

Bonus

  • Experience with mixed signal verification methodology in the context of PHY verification
  • Knowledge and familiarity with FPGA design flows including FPGA synthesis, place and route, timing closure and debug tools

Education and Experience

  • A minimum of 5+ years experience
  • Bachelor or Master’s degree in Computer or Electrical Engineering

The compensation range for this position is $165,000–$180,000. Salary ranges dependent on experience and location.

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