Sr CPU HW Engineer (CZ)
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Website Codasip
YOUR MAIN RESPONSIBILITIES:
- Innovate, develop, integrate, and evaluate state-of-the-art (micro-)architectural IP cores in Codasip Studio (primarily written in Codasip Studio’s processor high-level description language, CodAL) for the next generation of Processors and Accelerators based on the RISC-V architecture.
- Customize and enhance existing Codasip RISC-V IP cores to satisfy partners’/ customers’ requirements
- Participate on the the design verification and FPGA-based demonstrators.
- Participate in Codasip’s contribution to joint proof-of-concept demos with academic/ industrial partners.
- Report the technical results at international venues (e.g., RISC-V summit).
Requirements
- Over 5 years of recent and relevant hands-on experience with IP/Processor development.
- Strong background in Digital Design, computer architecture, and embedded systems.
- Experience with ASIC, FPGA design and IP verification (e.g., UVM).
- Preferred past experience in one or multiple of the following areas: AI, safety, and security.
- CodAL programming knowledge is not required but experience in HLS (e.g., C++/Matlab/SystemC) is needed.
- Experience with VHDL/Verilog, SystemVerilog.
- SW skills: C/ C++/ Assembly, HLS, and scripting languages (bash, Python).
- Fluent written and spoken English is essential. Czech is an advantage.
- Excellent communication skills, pragmatic, proactive, self-motivated, team player.
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