In IIP (Integrated Interconnect & Packaging) team, you will initiate novel package concepts, own and drive advanced package development, new product package structure and configuration optimization.
You will be responsible for 3DFabric technology research and development,, including InFO, CoWoS, and SoIC process/integration development for customer’s variety applications.
1. Develop advanced 3DIC (InFO, CoWoS, and SoIC) process and sustain baseline.
2. Package level reliability, failure mode analysis and improvement plan.
3. Customer technical interface, new tape out and lot handle.
4. Handover developed technologies to manufacturing groups for production.
1. Responsible for CVD / PVD / CMP / Lithography / Etch / Polymer / Bonding / Clean module development for 3DIC projects.
2. New technology, materials survey, and process improvement on 3DIC package structures.
3. Process development and tool transfer to mass-production development.
1. Conduct risk assessment and provide mitigation plan for IC packages by simulation and experiment.
2. Practice FEM and DOE in problem solving and path finding, particularly on packaging.
3. Continue improvement in simulation methodology, material modeling, and script automation.
1. Master’s degree or Ph.D. in Chemical Engineering, Material Science, Chemistry, Physics, Mechanical Engineering, or related Science or Engineering fields
2. Experienced in TV design or IC packaging is preferred
3. Good communication skills in Mandarin and English
4. Hands-on participation and a strong sense of ownership is required
5. Strong technical problem-solving and analytical skills
6. For simulation positions, mastered in FEM software, such as Ansys, LS-DYNA, Abaqus and others is required
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To view the job application please visit careers.tsmc.com.