Physical Design Engineer

Must possess at least 8 years’ experience of hands-on physical design

– Strong experience in block/full chip level floor-planning, placement techniques, power grid design and clock tree design

– Strong experience in STA and multi-mode, multi-scenario environments

– Expertise in EDA Tool Experience: > DC/DCT, RC/Genus, ICC/ICC2, Encounter/Innovus, PrimeTime-SI, StarXT, ICV, Conformal LEC, Redhawk

– Expertise in DRC-LVS closure with ICV or Calibre. (16nm experience is a plus ).

– Deep knowledge / understanding of physical effects in DSM technologies (28nm,16nm and below)

– Excellent knowledge of the complete RTL to GDS design flow for hierarchical designs.

– Good understanding of Reliability verification checks EM, IR etc.

– Proficiency in at least one of these scripting languages: Perl, TCL, Python.

– Low power flow (power gating, multi-VT, voltage islands, dynamic voltage scaling, body biasing, etc.

– Synthesis flow with involvement in multiple tape-outs.