Design & Verification Engineer_SMTS – SISW-MG
Website Siemens EDA
Roles & Responsibilities:
- Development of verification environments for emulation on standard protocol
- Suggest and prototype various verifications flows using Veloce
- Integration and qualification of various supported solutions like Questa, zero-in, codelink (Mentor Graphics provided solutions)
- Integration and qualification of various vertical solutions available with us e.g. various internal IP cores, hardware solutions with developed design
Requirement
- B.Tech/M.Tech from a reputed institute
- Having more than 3 years+ of Design and Verification
Skills required
- Protocol / Practical experience on any of the following protocol is necessary – o AMBA, o USB, o HDMI
- Experience in IP and SOC level verification using SV/UVM
- Added advantage if person knows c/c++/system c
- Knowledge of verification methodologies like UVM, OVM, TLM, Assertion, Coverage, co-simulation, co-verification
- Good communication skills as person needs to work with external interfaces
- FPGA synthesis knowledge and emulation experience is high positive
- Good scripting and automation knowledge is big plus for the role
Organization: Digital Industries
Company: Mentor Graphics (India) Private Limited
Experience Level: Experienced Professional
Job Type: Full-time
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To view the job application please visit jobs.siemens-info.com.
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