We’re confirming seats in Portland and Seattle for the Pacific Northwest leg of our worldwide 2019 SiFive Tech Symposiums. We are pleased to have Mentor, A Siemens Business as our co-host, and Lauterbach, a leader in microprocessor development tools, as our partner in both cities. The Portland symposium will take place Tuesday, October 22 at the Portland Community College. Our Seattle symposium will be on Wednesday, October 23 at thinkspace Seattle. All of the SiFive Tech Symposiums have been significantly instrumental in engaging the hardware community in the RISC-V ecosystem, and spearheading the emergence of new applications. We are constantly in awe of the brilliant minds that convene at these events. We thrive on watching intense conversations and the sharing of ideas between those already entrenched in RISC-V and others who are simply exploring design alternatives.
The symposiums in Portland and Seattle will both feature presentations by the RISC-V Foundation, SiFive, Mentor and Lauterbach, as well as other ecosystem partners and academic luminaries. There will also be a tutorials, demos and presentations on RISC-V developments tools, platforms, core IP and SoC IP. As always, we have arranged for plenty of time for networking.
- To view the agenda, and to confirm your seat in Portland, please click here.
- To view the agenda, and to confirm your seat in Seattle, please click here.
We look forward to seeing you!
SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 14 offices worldwide, SiFive has backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.
About the RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 325 members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. The Foundation has a Board of Directors comprising seven representatives from Bluespec, Inc.; Google; Microsemi; NVIDIA; NXP; University of California, Berkeley; and Western Digital.
In November 2018, the RISC-V Foundation announced a joint collaboration with the Linux Foundation. As part of this collaboration, the Linux Foundation will also provide an influx of resources for the RISC-V ecosystem, such as training programs, infrastructure tools, as well as community outreach, marketing and legal expertise.
Each year, the RISC-V Foundation hosts global events to bring the expansive ecosystem together to discuss current and prospective RISC-V projects and implementations, as well as collectively drive the future evolution of the instruction set architecture (ISA) forward. Event sessions feature leading technology companies and research institutions discussing the RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and much more. Learn more by visiting the Event Proceedings page.Share this post via: