RISC-V and Chiplets: A Panel Discussion

At the recent RISC-V Summit, the very last session was a panel about chiplets called Chiplets in the RISC-V Ecosystem. It was moderated by Calista Redmond, the CEO of RISC-V International. The panelists were:

• Laurent Moll, COO of Arteris
• Aniket Saha, VP of Product Management of Tenstorrent
• Dale Greenley, VP of Engineering of Ventana Microsystems
• Rob Aitken, Distinguished Architect of Synopsys

This is a slightly odd combination of topics to me. Obviously, you can put a RISC-V processor on a chiplet but the challenges are not really different from any other processor. But RISC-V is hot and so are chiplets, and companies like Ventana are combining them.

Let me give you a bit of background about the companies to put them in context:

• As you probably know, Arteris makes networks-on-chip (NoCs). It is a neutral company among chiplet vendors (and IP vendors).
• Tenstorrent is designing a portfolio of very high-performance multicore RISC-V chips
• Ventana has RISC-V IP but it also delivers it as chiplets
• Synopsys is obviously an EDA company but they announced RISC-V cores earlier in the summit

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The Actual Discussion

The first question from Calista was a softball asking what was the value of chiplets.

Dale said there was nothing specific about RISC-V for chiplets but the market decides when you do big monolithic things or chiplets. It depends on what a customer will pay you to do. “We provide both IP and chiplets, there is room for both.”

Aniket said that “doing chiplets is not cheap but doing chiplets and RISC-V is flexible and you can come up with hew products fast.”

Laurent went for production costs. NRE is very important to keep under control since not many people are building 100M parts. So there are more vendors involved and a complicated supply chain. An SoC is complex but chiplets are worse.

Rob pointed out heterogeneity like adding chiplets for RF and analog, having an optional accelerator, and so on. This potentially opens up new markets.

Calista went on to ask about where we are in automotive.

Aniket pointed out that automotive is very conservative and now they are aggressive about platforms that can scale from low end cars to high end cars. With chiplets, no one has really considered functional safety.

Rob went to aerospace (not quite automotive) and discussed how there is usually a fixed physical volume defined decades ago. It is hard to fit things in.

Laurent: Automotive companies are the ultimate catalog shoppers and chiplets let them take the best in AI, radar, infotainment, and so on.

How do you get the software to run?

Rob: if you make the system small, that is fine. But the automotive catalog shopping makes it harder.

Aniket: Related a statement “if you add it we won’t use it”. Automotive software stacks will support RISC-V in 5 years, which is fast. It took Arm 15 years to get there.

Q: What do we need for connectivity?

Laurent: It is very complex especially with people shopping around for chiplets. PHYs from different vendors, may be interoperable. Everyone is keen on UCIe. People want standards that make chiplets fit better.

Aniket complained that there are no standard design flows for chiplet. A big lack of standards.

Rob thinks we can come up with a standard flow but with different chiplets we don’t wan N different design flows.

Q: Where do you see things in 3-5 years?

Rob: we will be further along with different

“catalog shopping maybe depending on automotive OEMs. It will take a lot of industry effort. Any heterogenous stuff will take longer.

Aniket said chiplets will first be in the datacenter and then automotive. But first wave will be single vendor.

Summary

This is a combination of things that the participants said and my own opinions.

I think that for the time being, chiplet-based RISC-V designs will be single company effort (except, perhaps, for high-bandwidth-memory (HBM). It is too complex to build designs with multiple chiplets from different companies, interposers, and the network to connect them all, usually known as RDL.

Designs will be 2.5D not true 3D (where die are stacked on top of each other and communicate with thru-silicon-vias or TSVs) for the foreseeable future.

Automotive has its own set of challenges, in particular ensuring that chiplet-based designs are reliable in an environment with a lot of vibration. This will require extensive testing. Another issue is ensuring functional safety in an multi-die environment.

UCIe is promising and is somewhat based on PCIe. PCIe companies ensured reliability through plugfests. I don’t see how you can economically ensure UCIe interoperability in chiplets through a similar mechanism.

Finally, in addition to technical challenges, there are commercial challenges if we are to get to the nirvana of being able to purchase chiplets off-the-shelf and assemble them into systems at a reasonable cost. The biggest challenge is who will pay for and hold the inventory of chiplets. If all chiplets have to be manufactured on-demand then a lot of the advantages of a fast cycle time will be lost.

But RISC-V chiplets are certainly coming fast in the form of multi-die designs on 2.5D interposers built by a single company.

Also Read:

NoCs give architects flexibility in system-in RISC-V design

Pairing RISC-V cores with NoCs ties SoC protocols together

#60DAC Update from Arteris